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參數(shù)資料
| 型號： | AD9577BCPZ-RL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 25/44頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLK GEN PLL DUAL 40LFCSP |
| 標準包裝： | 2,500 |
| 系列： | PCI Express® (PCIe) |
| 類型： | 扇出緩沖器（分配），網絡時鐘發(fā)生器，多路復用器 |
| PLL： | 是 |
| 主要目的： | 以太網，PCI Express（PCIe），SONET/SDH |
| 輸入： | 時鐘，晶體 |
| 輸出： | LVCMOS，LVDS，LVPECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:5 |
| 差分 - 輸入:輸出： | 無/是 |
| 頻率 - 最大： | 637.5MHz |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 40-WFQFN 裸露焊盤，CSP |
| 供應商設備封裝： | 40-LFCSP-WQ（6x6） |
| 包裝： | 帶卷 (TR) |
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Data Sheet
AD9577
Rev. 0 | Page 31 of 44
Table 21.PLL2 Output Driver Format Control Bits,
Register DR1[5:3]
FORMAT2 (PLL2)
Register DR1[5:3]
OUT3P/OUT3N
OUT2P/OUT2N
000
LVPECL
001
LVDS
010
2 × CMOS
LVPECL
011
2 × CMOS
100
2 × CMOS
LVDS
101
LVPECL
LVDS
110
LVPECL
2 × CMOS
2 × CMOS
1 This indicates that the CMOS outputs are in phase; otherwise, they are in
antiphase.
LVDS uses a current mode output stage. The normal value
(default) for this current is 3.5 mA, which yields a 350 mV
output swing across a 100 Ω resistor. The LVDS outputs meet or
exceed all ANSI/TIA/EIA-644 specifications. The LVDS output
buffer should be terminated with a 100 Ω differential resistor
between the receiver input ports (see Figure 38). A recommended
termination circuit for the LVDS outputs is shown in Figure 38.
50
LVDS
100
LVDS
092
84-
042
Figure 38. LVDS Output Termination
See the AN-586 Application Note, LVDS Outputs for High Speed
A/D Converters, for more information about LVDS.
In a dc-coupled application, the LVPECL output buffer should
be terminated via a pair of 50 Ω resistors to a voltage of VCC 2 V.
This can be implemented by using potential dividers of 127 Ω
and 83 Ω between the supplies, as shown in Figure 39.
3.3V
50
SINGLE-ENDED
(NOT COUPLED)
3.3V
LVPECL
127
83
VT = VDD – 2V
LVPECL
0
928
4-
0
43
Figure 39. LVPECL DC-Coupled Termination
An alternative LVPECL termination scheme for dc-coupled
applications is shown Figure 40.
50
LVPECL
50
LVPECL
0
928
4-
0
44
Figure 40. LVPECL DC-Coupled Y-Termination
In ac-coupled applications, the LVPECL output stage needs a
pair of 200 Ω pull-down resistors to GND to provide a dc path for
the output stage emitter followers (see Figure 41). The receiver must
provide an additional 50 Ω single-ended input termination.
50
LVPECL
50
200
LVPECL
VTERM
0.1F
09
284
-045
Figure 41. LVPECL AC-Coupled Termination
REFERENCE OUTPUT BUFFER
A CMOS buffered copy of the reference input circuit signal is
available at the REFOUT pin. This buffer can be optionally
powered down by setting Register DR2[0], PDRefOut to Logic 0.
PLL1 INTEGER-N PLL
The upper PLL in Figure 32, PLL1, is an integer-N PLL with a
loop bandwidth of 140 kHz. The input frequency to the PLL
from the reference circuit is fPFD. The VCO frequency, fVCO1, is
programmed by setting the value for Na, according to
fVCO1 = fPFD × Na
(3)
where Na is programmable in the 80 to 131 range. The VCO
output frequency can tune over the 2.15 GHz to 2.55 GHz range to
integer multiples of the PFD input frequency only.
By setting each of the VCO divider (V0 and V1) and output
divider (D0 and D1) values, the VCO frequency can be divided
down to the required output frequency, independently, for each
of the output ports, OUT0 and OUT1. The fOUT0 frequency
presented to OUT0 can be set according to
D0
V0
Na
f
PFD
OUT
×
=
0
(4)
The frequency fOUT1 presented to OUT1 can be set according to
1
D
V
Na
f
PFD
OUT
×
=
(5)
The loop filters required for this PLL are integrated on chip.
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