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參數(shù)資料
| 型號： | AD9561JR |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 模擬信號調(diào)理 |
| 英文描述： | Pulse Width Modulator |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, PDSO28 |
| 封裝： | PLASTIC, SOIC-28 |
| 文件頁數(shù)： | 4/8頁 |
| 文件大?。?/td> | 273K |
| 代理商： | AD9561JR |
AD9561
–4–
REV. 0
THEORY OF OPERATION
General
The AD9561 is a mixed signal IC designed to provide high-
speed pulse width modulation in laser printers and copiers. It
uses high performance analog circuits to achieve high resolution
pulse control without requiring the excessively high clock rates
of an all digital solution.
Because of the sensitivity of analog circuits to digital crosstalk,
PCB layout is critical for achieving optimum results. Please read the
layout section at the end of this data sheet and follow suggestions
completely for best performance.
The AD9561 was designed to facilitate either higher effective
resolution or photo-realistic image reproduction on low cost
laser print platforms. Its 8-bit pulse width resolution and pulse
positioning capabilities combine to offer the highest level of gray
shading and resolution enhancement flexibility available. It
also includes an autocalibration circuit to minimize external
components, and eliminates an extra burden on the system
microprocessor.
The Functional Block Diagram illustrates the analog content,
comprising ramp generators, DACs and comparators that
generate a series of pulses. These pulses are combined in the
output logic to form PWM OUT pulses whose width is propor-
tional to the 8-bit DATA and whose position is determined by
the SEM/DEM and LEM/TEM inputs.
The AD9561 employs a proprietary ramp topology that
eliminates the loss of dynamic range at the ends of the ramp.
The Functional Block Diagram is shown for illustration purposes
only and does not represent the actual implementation.
Modulation Modes
Positioning the width controlled pulses at the beginning, middle
or end of the CLOCK period, as shown in Figure 2, adds
significantly to the flexibility of the AD9561. This is accom-
plished through control bit SEM/DEM and LEM/TEM. These
acronyms represent Single-Edge Modulation/Dual-Edge
Modulation and Leading-Edge Modulation/Trailing-Edge
Modulation. SEM/DEM and LEM/TEM are collectively
identified as CONTROL.
LEADING EDGE
MODULATION
TRAILING EDGE
MODULATION
DUAL EDGE
MODULATION
Figure 2. Modulation Modes
Pulse positioning within the CLOCK period is defined by the
following table:
Table I. Truth Table
SEM/DEM
LEM/TEM
Alignment
1
1
0
1
0
X
LEM
TEM
DEM
Single-Edge Modulation offers two options in which one edge is
modulated while the other remains fixed relative to the CLOCK.
For Leading-Edge Modulation, the rising edge of the pulse is
delayed from the leading edge of the CLOCK proportional to
DATA, and the falling edge remains fixed at the end of the
CLOCK period. This may also be called “right-hand justified.”
Similarly, Trailing-Edge Modulation has the rising edge fixed
on the beginning of the CLOCK period and the falling edge
delayed proportional to DATA. This can be called “l(fā)eft-hand
justified.”
Dual-Edge Modulation is often called “center justified” because
the delay of both edges varies relative to the CLOCK. With
increasing values for DATA, pulse width increases with its
center remaining constant proportional to the CLOCK.
Like DATA, modulation control inputs SEM/DEM, and
LEM/TEM can be updated at the CLOCK rate up to 60 MHz.
Figure 1. Pulse Pattern Example
N+1
N+1
PULSE N
PULSE
N+1
CLOCK
DATA
CONTROL
OUTPUT
N
FF, XX
100%
DNC
0%
DNC
75%
TEM
75%
DEM
87%
LEM
75%
DEM
75%
DEM
50%
DEM
25%
DEM
0%
DNC
00, XX
C0, 10
C0, 0X
C0, 0X
80, 0X
40, 0X
00, XX
C0, 0X
E0, 11
FF, XX
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相關(guān)代理商/技術(shù)參數(shù) |
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