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參數(shù)資料
| 型號(hào)： | AD9561JR |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 模擬信號(hào)調(diào)理 |
| 英文描述： | Pulse Width Modulator |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, PDSO28 |
| 封裝： | PLASTIC, SOIC-28 |
| 文件頁數(shù)： | 2/8頁 |
| 文件大?。?/td> | 273K |
| 代理商： | AD9561JR |
–2–
REV. 0
AD9561–SPECIFICATIONS
(+V
S
= +5 V; R
= 715
V
, CLOCK = 20 MHz unless otherwise noted)
AD9561JR
Parameter
Temp
Min
Typ
Max
Units
RESOLUTION
8
Bits
ACCURACY (@ 20 MHz)
Differential Nonlinearity
Integral Linearity
1
Odd/Even Pulse Mismatch
2
+25
°
C
+25
°
C
+25
°
C
±
0.5
±
1.5
±
0.75
±
2
±
4
LSB
LSB
LSB
DIGITAL INPUTS
Logic “1” Voltage
Logic “0” Voltage
Input Current
Input Capacitance
Data Setup Time
Data Hold Time
Minimum Clock Pulse Width (HIGH)
Full
Full
Full
+25
°
C
Full
Full
Full
2.0
V
V
μ
A
pF
ns
ns
ns
0.8
±
1
5
0.3
0.3
6
2.0
2.0
DYNAMIC PERFORMANCE
Maximum Trigger Rate
Minimum Propagation Delay (t
PD
)
3
Minimum Propagation Delay TC
Output Pulse Width @ Code 25
4
Output Pulse Width @ Code 255
Output Rise Time
5, 6
Output Fall Time
5, 6
RETRACE Propagation Delay
Full
+25
°
C
Full
Full
Full
Full
Full
Full
60
12
MHz
ns
ps/
°
C
ns
% Clock
ns
ns
ns
20
60
5
100
1.8
1.8
6
28
3
3
PWM OUTPUT
Logic “1” Voltage
5, 6
Logic “0” Voltage
5, 6
Full
Full
4.6
V
V
0.4
CAL OUT
Logic “1” Voltage
Logic “0” Voltage
Full
Full
4.6
V
V
0.4
POWER SUPPLY
7
Positive Supply Current (+5.0 V)
Power Dissipation
Power Reduce Current
Power Reduce Dissipation
Power Supply Rejection Ratio
Propagation Delay Sensitivity (TEM)
8
Full
Full
Full
Full
140
700
70
350
170
850
85
425
mA
mW
mA
mW
+25
°
C
1.5
ns/V
NOTES
1
Best Fit between codes 25 and 230. INL is very layout sensitive.
2
Due to linearity mismatch in dual ramps.
3
Measured from rising edge of clock to transition of Codes 0 to 255.
4
Minimum pulse width (at 20 MHz) limited by rise time. Pulse width for Code 25 will be greater when CLOCK < 20 MHz.
5
Output load = 10 pF and 2 mA source/sink.
6
Load conditions to test output drive capability. Linearity will degrade with either capacitive or current loading. Best linearity obtained driving a single CMOS input.
7
All performance specifications valid when supply maintained at +5 V,
±
5%.
8
Tested from +4.75 V to +5.25 V.
Specification subject to change without notice.
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