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參數(shù)資料
| 型號： | AD9561JR-REEL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 模擬信號調(diào)理 |
| 英文描述： | Pulse Width Modulator |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, PDSO28 |
| 封裝： | PLASTIC, SOIC-28 |
| 文件頁數(shù)： | 7/8頁 |
| 文件大?。?/td> | 273K |
| 代理商： | AD9561JR-REEL |
AD9561
–7–
REV. 0
Grounding and Bypassing
Because the AD9561 uses analog circuits to achieve its superb
gray scale resolution, caution must be exercised when incorpo-
rating it into the mostly digital controller card for a printer.
Achieving the accuracy designed into the AD9561 requires that
interference due to improper grounding, power supply noise and
digital coupling be minimized by following good layout practices.
It is strongly urged that all following recommendations be
followed.
Factory characterization proves that a single ground plane
dedicated to the AD9561 is most effective. This is atypical of
many mixed signal circuits that use separate analog and digital
grounds. Due to the operating speed of the AD9561, separate
grounds result in erratic performance, which is eliminated by
using a single isolated ground plane. This is because the DATA
“l(fā)ow” value can be different from the ground value of the
AD9561. All pins on the AD9561 labeled GROUND should
be connected to the single dedicated ground plane. For best
results, it is suggested that this plane be in the first interior layer
under the IC. To assure logic level compatibility from the drive
circuits to the AD9561, a single connection to the board’s main
ground is necessary.
The connection between the dedicated ground plane and the
board’s main ground should be parallel to the path of the digital
signals interfacing to the AD9561. High frequency return current
seeks the path most parallel to the signal current. Whenever a
parallel path does not exist, ground bounce results.
CLOCK, DATA and CONTROL signal traces should run
from the drive logic to the AD9561 in a group parallel to the
connection between the system ground and the AD9561
ground. Using more than one signal plane will permit these
traces to be as close to the ground interconnection as possible.
This results in lowest impedance ground return and minimum
ground interference due to digital switching.
Attention to subtle layout characteristics can yield significant
improvement in performance of high speed mixed signal ICs.
The AD9561 pinouts were chosen for maximum isolation of
sensitive pins such as R
SET
. The Pin 1 end of the IC should be
oriented toward the source of the high speed digital inputs.
This will help assure that these signal runs are short, with
essentially the same length, thus having equal propagation
delays. Most importantly, it will facilitate orienting traces to
minimize coupling.
High speed digital traces including DATA, CLOCK, SEM/
DEM, LEM/TEM and the OUTPUT should not pass under the
body of the IC. The CLOCK, in particular, should enter
perpendicular to the IC.
For best results, the OUTPUT trace should exit perpendicular
to the IC and pass through a via to a signal layer under the
ground plane. This trace or any resistor or other component
of the output circuit should not be parallel to R
SET
as electro-
magnetic coupling can occur, causing the ramp current reference
to be noisy and linearity to deteriorate.
Optimally, R
SET
should be a chip resistor located on the same
side of the board as the AD9561. It should be located close to
Pin 14, without being close to the other IC pins. R
SET
should
be on the top of the board with the AD9561 with no vias to add
stray reactance and additional coupling paths.
To reiterate the key layout considerations, high speed
digital traces should not be located near the R
SET
pin or
under the center of the IC body.
A final interface consideration relates to rise/fall time of
the high speed signals. Some logic families have rise and
fall times as fast as 2 V/ns. This can result in on-chip
parasitic coupling of these signals into the analog section.
The undesirable effect can be eliminated by inserting
series resistors in the DATA, SEM/DEM and LEM/
TEM connections. These resistors, in conjunction with the
capacitance of the input pin and bond pad, will form a low
pass filter to limit slew rate of the signals. The value of
these resistors should be chosen based on trading off slower
rise and fall time to possible interference to set up and hold
times for faster clock rates.
Power supply noise can also disrupt the linear circuits of
the AD9561. Since switching power supplies are becoming
the norm in most systems, caution should be exercised to
minimize switching noise reaching the AD9561. The IC is
designed for maximum power supply rejection. However,
frequency content of switching supply noise often exceeds
the frequency range of highest rejection. The preferred
method would be to use a linear regulator from a higher
supply voltage. If this is not practical, insert a ferrite bead
in series with the supply connection. If possible, a V
DD
plane or a substantial width trace should connect V
DD
to
Pin 7 first and then connect to each of the other V
DD
pins
with wide traces. Thorough decoupling will complete a low
pass filter for the supply.
All V
DD
connections should be connected together. 0.1
μ
F
chip capacitors should be connected as closely as possible
to each V
DD
pin to the dedicated ground plane. Laboratory
results indicate that performance is maximized when these
chip capacitors are mounted on the same side of the PC
card as the AD9561. If mounting chip components on the
same side as the AD9561 is not a preferred manufacturing
method, due consideration is encouraged to make an excep-
tion, at least in the case of R
SET
and as many decoupling
capacitors as practical. Additionally, a 10
μ
F tantalum
capacitor should decouple the supply on the AD9561 side
of the regulator or ferrite bead, also to the dedicated
ground plane.
For a recommended layout, see the AD9561/PCB data
sheet. A copy can be obtained by calling Applications
Support at 1-800-ANALOGD.
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