For fVCO = 3888 MHz, an obvious" />
參數(shù)資料
型號(hào)： AD9553BCPZ-REEL7
廠商： Analog Devices Inc
文件頁數(shù)： 21/44頁
文件大?。?/td> 0K
描述： IC INTEGER-N CLCK GEN 32LFCSP
標(biāo)準(zhǔn)包裝： 1,500
類型： 時(shí)鐘/頻率轉(zhuǎn)換器
PLL： 是
主要目的： 以太網(wǎng)，GPON，SONET/SHD，T1/E1
輸入： CMOS，LVDS，晶體
輸出： CMOS，LVDS，LVPECL
電路數(shù)： 1
比率 - 輸入:輸出： 1:2
差分 - 輸入:輸出： 是/是
頻率 - 最大： 810MHz
電源電壓： 3.135 V ~ 3.465 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 32-WFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 32-LFCSP（5x5）
包裝： 帶卷 (TR)
配用： AD9553/PCBZ-ND - BOARD EVAL FOR AD9553
AD9553
Rev. A | Page 28 of 44
5. Determine N, K, and R.
For fVCO = 3888 MHz, an obvious solution is K = 1, R = 125,
and N = 3888, which satisfies the constraint on both N and
R, and yields FPFD = 1 MHz.
For fVCO = 3732.48 MHz, an obvious solution is N =
373,248, K = 1, and R = 12,500. This choice, however,
violates the constraints on both N and R in Step 3.
A simple remedy is to divide both N and R by a common
factor. In this particular case, four is the greatest common
factor of N and R. Dividing by four leads to N = 93,312,
K = 1, and R = 3125 (K = 1), satisfying the constraint on
N and R, and yielding FPFD = 40 kHz. Note that to match
the values given in the Preset Frequencies section, FPFD
must be 16 kHz. To accomplish this, keep R = 3125, but
choose K = 2/5 (see Table 14). This changes N to 233,280,
which agrees with Table 16.
For fVCO = 3421.44 MHz, an obvious solution is
N = 342,144
K = 1
R = 12,500.
As with the case for fVCO = 3732.48 MHz, this choice
violates the constraints on both N and R in Step 3. Once
again, the greatest common factor of N and R is four,
leading to N = 85,536, K = 1, and R = 3125 (K = 1),
yielding FPFD = 40 kHz.
In summary, if choosing fVCO = 3421.44 MHz, then a
possible solution is
P0 = 11
P1 = 2
N = 85,536
R = 3,125
K = 1
FPFD = 40 kHz
If one chooses fVCO = 3732.48 MHz, then the solution set
that matches the tables in the Preset Frequencies section is
P0 = 6
P1 = 4
N = 233,280
R = 3,125
K = 2/5
FPFD = 16 kHz
If choosing fVCO = 3888 MHz, then a possible solution is
P0 = 5
P1 = 5
N = 3888
R = 125
K = 1
FPFD = 1 MHz
6. If applicable, determine RXO, the XTAL divider value.
The value of RXO depends on the value of fREF, K, and R
from Step 5, as follows:
×
=
K
R
f
R
REF
XO
6
10
50
Given that fREF = 125 MHz, the two results from Step 5 lead to
RXO = 3125 (for R = 3125 and K = 2/5)
RXO = 50 (for R = 125 and K = 1)
LOW DROPOUT (LDO) REGULATORS
The AD9553 is powered from a single 3.3 V supply and contains
on-chip LDO regulators for each function to eliminate the need
for external LDOs. To ensure optimal performance, each LDO
output should have a 0201-sized 0.47 μF capacitor connected
between its access pin and ground. In addition, double vias to
ground for these capacitors minimize the parasitic resistance and
inductance.
AUTOMATIC POWER-ON RESET
The AD9553 has an internal power-on reset circuit (see Figure 33).
At power-up, an 800 pF capacitor momentarily holds a Logic 0
at the active low input of the reset circuitry. This ensures that the
device is held in a reset state (~250 s) until the capacitor charges
sufficiently via the 100 k pull-up resistor and 200 k series
resistor. Note that when using a low impedance source to drive
the RESET pin, be sure that the source is either tristate or Logic 0
at power-up. Otherwise, the device may not calibrate properly.
15
RESET
200k
100k
800pF
VDD
RESET
CIRCUITRY
AD9553
08565-
105
Figure 33. Power-On Reset
Provided an input reference signal is present at the REFA,
REFB, or XTAL pin, the device automatically performs a VCO
calibration during power-up. If the input reference signal is not
present, VCO calibration fails and the PLL does not lock. As
soon as an input reference signal is present, the user must reset
the device to initiate the automatic VCO calibration process.
Any change to the preset frequency selection pins requires the
user to reset the device. This is necessary to initiate the automatic
VCO calibration process.
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