參數(shù)資料
型號(hào)： AD9540BCPZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 16/32頁(yè)
文件大小： 0K
描述： IC CLOCK GENERATOR PLL 48-LFCSP
標(biāo)準(zhǔn)包裝： 1
類型： 時(shí)鐘發(fā)生器
PLL： 是
輸入： 時(shí)鐘
輸出： CML，PECL
電路數(shù)： 1
比率 - 輸入:輸出： 2:2
差分 - 輸入:輸出： 是/是
頻率 - 最大： 655MHz
除法器/乘法器： 是/無(wú)
電源電壓： 1.71 V ~ 1.89 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 48-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 48-LFCSP-VQ（7x7）
包裝： 托盤
產(chǎn)品目錄頁(yè)面： 776 (CN2011-ZH PDF)
AD9540
Rev. A | Page 23 of 32
INSTRUCTION BYTE
The instruction byte contains the following information.
MSB
LSB
D7
D6
D5
D4
D3
D2
D1
D0
R/Wb
X
A4
A3
A2
A1
A0
R/Wb—Bit 7 of the instruction byte determines whether a read
or write data transfer occurs after the instruction byte write.
Logic 1 indicates a read operation. Logic 0 indicates a write
operation.
X, X—Bit 6 and Bit 5 of the instruction byte are don’t care.
A4, A3, A2, A1, and A0—Bit 4, Bit 3, Bit 2, Bit 1, and Bit 0 of
the instruction byte determine which register is accessed during
the data transfer portion of the communications cycle.
SERIAL INTERFACE PORT PIN DESCRIPTION
SCLK—Serial Clock. The serial clock pin is used to synchronize
data to and from the AD9540 and to run the internal state
machines. The SCLK maximum frequency is 25 MHz.
CS—Chip Select Bar. CS is the active low input that allows more
than one device on the same serial communications line. The
SDO pin and SDI/O pin go to a high impedance state when this
input is high. If driven high during any communications cycle,
that cycle is suspended until CS is reactivated low. Chip select
can be tied low in systems that maintain control of SCLK.
SDI/O—Serial Data Input/Output. Data is always written to the
AD9540 on this pin. However, this pin can be used as a
bidirectional data line. CFR1[7] controls the configuration of
this pin. The default value (0) configures the SDI/O pin as
bidirectional.
SDO—Serial Data Output. Data is read from this pin for
protocols that use separate lines for transmitting and receiving
data. When the AD9540 operates in a single bidirectional I/O
mode, this pin does not output data and is set to a high
impedance state.
I/O_RESET—A high signal on this pin resets the I/O port state
machines without affecting the addressable registers’ contents.
An active high input on the I/O_RESET pin causes the current
communication cycle to abort. After I/O_RESET returns low
(0), another communication cycle can begin, starting with the
instruction byte write. Note that when not in use, this pin
should be forced low, because it floats to the threshold value.
MSB/LSB TRANSFERS
The AD9540 serial port can support both most significant bit
(MSB) first or least significant bit (LSB) first data formats. This
functionality is controlled by the LSB first bit in Control
Register 1 (CFR1[15]). The default value of this bit is low (MSB
first). When CFR1[15] is set high, the AD9540 serial port is in
LSB first format. The instruction byte must be written in the
format indicated by CFR1[15]. If the AD9540 is in LSB first
mode, the instruction byte must be written from LSB to MSB.
However, the instruction byte phase of the communication
cycle still precedes the data transfer cycle.
For MSB first operation, all data written to (or read from) the
AD9540 are in MSB first order. If the LSB mode is active, all
data written to (or read from) the AD9540 are in LSB first
order.
CS
SCLK
SDI/O
TPRE
TDSU
TSCLKW
TDHLD
SECOND BIT
FIRST BIT
SYMBOL
TPRE
TSCLKW
TDSU
TDHLD
MIN
6ns
40ns
6.5ns
0ns
DEFINITION
CS SETUP TIME
PERIOD OF SERIAL DATA CLOCK (WRITE)
SERIAL DATA SETUP TIME
SERIAL DATA HOLD TIME
04947-
039
Figure 43. Timing Diagram for Data Write to AD9540
TDV
FIRST BIT
SECOND BIT
SDI/O
SDO
SCLK
CS
SYMBOL
TDV
TSCLKR
MAX
40ns
400ns
DEFINITION
DATA VALID TIME
PERIOD OF SERIAL DATA CLOCK (READ)
04947-040
TSCLKR
Figure 44. Timing Diagram for Data Read from AD9540
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