參數(shù)資料
型號: AD9522-3BCPZ-REEL7
廠商: Analog Devices Inc
文件頁數(shù): 59/84頁
文件大?。?/td> 0K
描述: IC CLOCK GEN 2GHZ VCO 64LFCSP
標(biāo)準(zhǔn)包裝: 750
類型: 時鐘發(fā)生器,扇出配送
PLL:
輸入: CMOS,LVDS,LVPECL
輸出: CMOS,LVDS
電路數(shù): 1
比率 - 輸入:輸出: 2:12,2:24
差分 - 輸入:輸出: 是/是
頻率 - 最大: 2.25GHz
除法器/乘法器: 是/無
電源電壓: 3.135 V ~ 3.465 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 64-VFQFN 裸露焊盤,CSP
供應(yīng)商設(shè)備封裝: 64-LFCSP-VQ(9x9)
包裝: 帶卷 (TR)
AD9522-3
Rev. 0 | Page 62 of 84
Addr
(Hex)
Parameter
Bit 7 (MSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0 (LSB)
Default
Value
(Hex)
01E
PLL_CTRL_9
Unused
External zero delay
feedback
channel divider select
Enable
external
zero delay
Enable
zero delay
Unused
00
01F
PLL_Readback
(read-only)
Unused
VCO cal
finished
Holdover
active
REF2
selected
VCO freq >
threshold
REF2
freq >
threshold
REF1 freq >
threshold
Digital lock
detect
N/A
Output Driver Control
0F0
OUT0 control
OUT0 format
OUT0 CMOS
configuration
OUT0 polarity
OUT0 LVDS
differential voltage
OUT0
LVDS
power-down
62
0F1
OUT1 control
OUT1 format
OUT1 CMOS
configuration
OUT1 polarity
OUT1 LVDS
differential voltage
OUT1
LVDS
power-down
62
0F2
OUT2 control
OUT2 format
OUT2 CMOS
configuration
OUT2 polarity
OUT2 LVDS
differential voltage
OUT2
LVDS
power-down
62
0F3
OUT3 control
OUT3 format
OUT3 CMOS
configuration
OUT3 polarity
OUT3 LVDS
differential voltage
OUT3
LVDS
power-down
62
0F4
OUT4 control
OUT4 format
OUT4 CMOS
configuration
OUT4 polarity
OUT4 LVDS
differential voltage
OUT4
LVDS
power-down
62
0F5
OUT5 control
OUT5 format
OUT5 CMOS
configuration
OUT5 polarity
OUT5 LVDS
differential voltage
OUT5
LVDS
power-down
62
0F6
OUT6 control
OUT6 format
OUT6 CMOS
configuration
OUT6 polarity
OUT6 LVDS
differential voltage
OUT6
LVDS
power-down
62
0F7
OUT7 control
OUT7 format
OUT7 CMOS
configuration
OUT7 polarity
OUT7 LVDS
differential voltage
OUT7
LVDS
power-down
62
0F8
OUT8 control
OUT8 format
OUT8 CMOS
configuration
OUT8 polarity
OUT8 LVDS
differential voltage
OUT8
LVDS
power-down
62
0F9
OUT9 control
OUT9 format
OUT9 CMOS
configuration
OUT9 polarity
OUT9 LVDS
differential voltage
OUT9
LVDS
power-down
62
0FA
OUT10 control
OUT10 format
OUT10 CMOS
configuration
OUT10 polarity
OUT10 LVDS
differential voltage
OUT10
LVDS
power-down
62
0FB
OUT11 control
OUT11 format
OUT11 CMOS
configuration
OUT11 polarity
OUT11 LVDS
differential voltage
OUT11
LVDS
power-down
62
0FC
Enable output
on CSDLD
CSDLD En
OUT7
CSDLD En
OUT6
CSDLD En
OUT5
CSDLD En
OUT4
CSDLD En
OUT3
CSDLD En
OUT2
CSDLD En
OUT1
CSDLD En
OUT0
00
0FD
Enable output
on CSDLD
Unused
CSDLD En
OUT11
CSDLD En
OUT10
CSDLD En
OUT9
CSDLD En
OUT8
00
0FE
to
18F
Unused
00
LVDS Channel Dividers
190
Divider 0 (PECL)
Divider 0 low cycles
Divider 0 high cycles
77
191
Divider 0
bypass
Divider 0
ignore
SYNC
Divider 0
force
high
Divider 0
start high
Divider 0
phase offset
00
192
Unused
Channel 0
power-
down
Reserved
Disable
Divider 0
DCC
00
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