參數(shù)資料
型號(hào)： AD9520-3BCPZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 55/80頁(yè)
文件大小： 0K
描述： IC CLOCK GEN 2GHZ VCO 64LFCSP
設(shè)計(jì)資源： Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers (CN0121)
Phase Coherent FSK Modulator (CN0186)
標(biāo)準(zhǔn)包裝： 1
類型： 時(shí)鐘發(fā)生器，扇出配送
PLL： 是
輸入： CMOS，LVDS，LVPECL
輸出： CMOS，LVPECL
電路數(shù)： 1
比率 - 輸入:輸出： 2:12，2:24
差分 - 輸入:輸出： 是/是
頻率 - 最大： 2.25GHz
除法器/乘法器： 是/無
電源電壓： 3.135 V ~ 3.465 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 64-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 64-LFCSP-VQ（9x9）
包裝： 托盤
產(chǎn)品目錄頁(yè)面： 776 (CN2011-ZH PDF)
Data Sheet
AD9520-3
Rev. A | Page 59 of 80
PROGRAMMING THE EEPROM BUFFER SEGMENT
The EEPROM buffer segment is a register space on the AD9520.
The user can specify which groups of registers are stored to the
EEPROM during EEPROM programming. Note that programming
this register space is optional. The default power-up values for the
EEPROM buffer segment allow storage of all the AD9520 register
values from Register 0x000 to Register 0x231 to the EEPROM.
As an example, a user might want to load only the output driver
settings from the EEPROM without disturbing the PLL register
settings currently stored in the AD9520. The user can alter the
EEPROM buffer segment to include only the registers that apply
to the output drivers and exclude the registers that apply to the
PLL configuration.
There are two parts to the EEPROM buffer segment: register
section definition groups and operational codes. Table 48 shows
an example of the EEPROM buffer segment.
Register Section Definition Group
Note that the AD9520 register map is noncontiguous, and the
EEPROM is only 512 bytes long. The register section definition
group tells the EEPROM controller how the AD9520 register map
is segmented. Each register section definition group contains the
starting address and number of bytes to be written to EEPROM.
The register section definition group defines a continuous register
section for the EEPROM profile. It consists of three bytes. The first
byte defines how many continuous register bytes are in this
group. If the user writes 0x000 to the first byte, it means that
there is only one byte in this group. If the user writes 0x001, it
means that there are two bytes in this group. The maximum
number of registers in one group is 128. The next two bytes are
the low byte and high byte, respectively, of the 16-bit memory
address of the first register in this group.
Operational Codes
There are three operational codes: IO_UPDATE, end-of-data, and
pseudo-end-of-data. It is important that the EEPROM buffer
segment always have either an end-of-data or a pseudo-end-of-
data operational code and that an IO_UPDATE operational code
appear at least once before the end-of-data operational code.
IO_UPDATE (Operational Code 0x80)
The EEPROM controller uses this operational code to generate
an IO_UPDATE signal to update the active control register
bank from the buffer register bank during the download process.
At a minimum, there should be at least one IO_UPDATE
operational code after the end of the final register section definition
group. This code is needed so that at least one IO_UPDATE occurs
after all of the AD9520 registers are loaded when the EEPROM
is read. If this operational code is absent during a write to the
EEPROM, the register values loaded from the EEPROM are not
transferred to the active register space, and these values do not
take effect after they are loaded from the EEPROM to the AD9520.
End-of-Data (Operational Code 0xFF)
The EEPROM controller uses this operational code to terminate
the data transfer process between EEPROM and the control
register during the upload and download process. The last item
appearing in the EEPROM buffer segment should be either this
operational code or the pseudo-end-of-data operational code.
Pseudo-End-of-Data (Operational Code 0xFE)
The AD9520 EEPROM buffer segment has 23 bytes that can
contain up to seven register section definition groups. If the user
wants to define more than seven register section definition groups,
the pseudo-end-of-data operational code can be used. During
the upload process, when the EEPROM controller receives the
pseudo-end-of-data operational code, it halts the data transfer
process, clears the REG2EEPROM bit, and enables the AD9520
serial port. The user can then program the EEPROM buffer
segment again and reinitiate the data transfer process by setting
the REG2EEPROM bit (Register 0xB03[0]) to 1b and the
IO_UPDATE bit (Register 0x232[0]) to 1b. The internal IC master
then begins writing to the EEPROM starting from the EEPROM
address held from the last writing.
This sequence provides the user with more discrete instructions
that can be written to the EEPROM than would otherwise be
possible due to the limited size of the EEPROM buffer segment.
It also allows for the same register to be written multiple times
with a different value each time.
Table 48. Example of the EEPROM Buffer Segment
Reg Addr (Hex)
Bit 7 (MSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0 (LSB)
Start EEPROM Buffer Segment
0xA00
0
Number of bytes [6:0] of the first group of registers
0xA01
Address [15:8] of the first group of registers
0xA02
Address [7:0] of the first group of registers
0xA03
0
Number of bytes [6:0] of the second group of registers
0xA04
Address [15:8] of the second group of registers
0xA05
Address [7:0] of the second group of registers
0xA06
0
Number of bytes [6:0] of the third group of registers
0xA07
Address [15:8] of the third group of registers
0xA08
Address [7:0] of the third group of registers
0xA09
IO_UPDATE operational code (0x80)
0xA0A
End-of-data operational code (0xFF)
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AD9520-3BCPZ-REEL7 功能描述:IC CLOCK GEN 2GHZ VCO 64LFCSP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:2,000 系列:- 類型:PLL 時(shí)鐘發(fā)生器 PLL:帶旁路 輸入:LVCMOS，LVPECL 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:2:11 差分 - 輸入:輸出:是/無 頻率 - 最大:240MHz 除法器/乘法器:是/無 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:32-LQFP 供應(yīng)商設(shè)備封裝:32-TQFP（7x7） 包裝:帶卷 (TR)
AD9520-4 制造商:AD 制造商全稱:Analog Devices 功能描述:12 LVPECL/24 CMOS Output Clock Generator with Integrated 1.6 GHz VCO
AD9520-4/PCBZ 功能描述:BOARD EVAL FOR AD9520-4 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評(píng)估演示板和套件 系列:- 標(biāo)準(zhǔn)包裝:1 系列:PSoC® 主要目的:電源管理，熱管理 嵌入式:- 已用 IC / 零件:- 主要屬性:- 次要屬性:- 已供物品:板，CD，電源
AD9520-4BCPZ 功能描述:IC CLOCK GEN 1.6GHZ VCO 64LFCSP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:2,000 系列:- 類型:PLL 頻率合成器 PLL:是 輸入:晶體 輸出:時(shí)鐘 電路數(shù):1 比率 - 輸入:輸出:1:1 差分 - 輸入:輸出:無/無 頻率 - 最大:1GHz 除法器/乘法器:是/無 電源電壓:4.5 V ~ 5.5 V 工作溫度:-20°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-LSSOP（0.175"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-SSOP 包裝:帶卷 (TR) 其它名稱:NJW1504V-TE1-NDNJW1504V-TE1TR
AD9520-4BCPZ-REEL7 功能描述:IC CLOCK GEN 1.6GHZ VCO 64LFCSP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:2,000 系列:- 類型:PLL 時(shí)鐘發(fā)生器 PLL:帶旁路 輸入:LVCMOS，LVPECL 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:2:11 差分 - 輸入:輸出:是/無 頻率 - 最大:240MHz 除法器/乘法器:是/無 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:32-LQFP 供應(yīng)商設(shè)備封裝:32-TQFP（7x7） 包裝:帶卷 (TR)
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