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| 型號： | AD9520-3/PCBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 73/80頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL AD9520-3 |
| 設(shè)計資源： | Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers (CN0121) Phase Coherent FSK Modulator (CN0186) AD9520 Eval Brd Schematic AD9520 BOM |
| 標準包裝： | 1 |
| 主要目的： | 計時，時鐘發(fā)生器 |
| 已用 IC / 零件： | AD9520-3 |
| 已供物品： | 板 |
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Data Sheet
AD9520-3
Rev. A | Page 75 of 80
Table 58. System
Reg.
Addr.
(Hex) Bits
Name
Description
0x230 [7:4] Unused
Unused.
3
Disable power on SYNC
Powers on SYNC mode. Used to disable the antiruntpulse circuitry.
0: enables the antiruntpulse circuitry (default).
1: disables the antiruntpulse circuitry.
2
Power down SYNC
Powers down the SYNC function.
0: normal operation of the SYNC function (default).
1: powers down SYNC circuitry.
1
Power down distribution
reference
Powers down the reference for the distribution section.
0: normal operation of the reference for the distribution section (default).
1: powers down the reference for the distribution section.
0
Soft SYNC
The soft SYNC bit works in the same way as the SYNC pin, except that the polarity of the bit is
reversed. That is, a high level forces selected channels into a predetermined static state, and a 1b-
to-0b transition triggers a SYNC.
0: same as SYNC pin high.
1: same as SYNC pin low.
Table 59. Update All Registers
Reg.
Addr.
(Hex) Bits
Name
Description
0x232 [7:1] Unused
Unused.
0
IO_UPDATE
This bit must be set to 1b to transfer the contents of the buffer registers into the active registers.
This transfer occurs on the next SCLK rising edge. This bit is self-clearing; that is, it does not have to be set
back to 0b.
1 (self-clearing): updates all active registers to the contents of the buffer registers.
Table 60. EEPROM Buffer Segment
Reg
Addr
(Hex) Bits Name
Description
0xA00
to
0xAFF
EEPROM buffer segment
The EEPROM buffer segment section stores the starting address and number of bytes that are to be
stored and then read back to and from the EEPROM. Because the AD9520 register space is
noncontiguous, the EEPROM controller uses the starting address and number of bytes in the
AD9520 register space to store and retrieve from the EEPROM.
There are two types of entries in the EEPROM buffer segment: data transfers and operational codes.
For a data transfer, Bit 7 of the command byte is set to 0b. The remaining seven bits are the size of
the transfer, minus 1 (that is, 0x01 indicates a 2-byte transfer). The starting address (MSB first) of the
transfer is contained in the two bytes of the EEPROM buffer segment that immediately follow the
data transfer command.
For an operational code, Bit 7 of the command byte is set to 1b and is a special instruction for the
EEPROM controller. There are two operational codes: IO_UPDATE and end of data. The IO_UPDATE
operational code instructs the EEPROM controller to transfer the AD9520 register values into the
active register space (and is functionally equivalent to writing 0x01 to Register 0x232). The end-of-
data operational code informs the EEPROM controller that the end of data has been reached and to
terminate the transfer. The last byte of the EEPROM buffer segment must contain an end-of-data
operational code.
Using the on-chip default setting of the EEPROM buffer segment registers, the EEPROM controller
transfers all register values to/from the EEPROM, and an IO_UPDATE is issued after transfer.
Therefore, the user does not normally need to alter the EEPROM buffer segment.
See the Programming the EEPROM Buffer Segment section for more information.
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