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| 型號： | AD9518-1ABCPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 34/64頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK GEN 6CH 2GHZ 48LFCSP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 時鐘發(fā)生器，扇出配送 |
| PLL： | 是 |
| 輸入： | CMOS，LVDS，LVPECL |
| 輸出： | LVPECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:6 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 2.65GHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 48-LFCSP-VQ（7x7） |
| 包裝： | 托盤 |
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AD9518-1
Data Sheet
Rev. C | Page 4 of 64
SPECIFICATIONS
Typical values are given for VS = VS_LVPECL = 3.3 V ± 5%; VS ≤ VCP ≤ 5.25 V; TA = 25°C; RSET = 4.12 k; CPRSET = 5.1 k, unless otherwise noted.
Minimum and maximum values are given over full VS and TA (40°C to +85°C) variation.
POWER SUPPLY REQUIREMENTS
Table 1.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
VS
3.135
3.3
3.465
V
3.3 V ± 5%
VS_LVPECL
2.375
VS
V
Nominally 2.5 V to 3.3 V ± 5%
VCP
VS
5.25
V
Nominally 3.3 V to 5.0 V ± 5%
RSET Pin Resistor
4.12
k
Sets internal biasing currents; connect to ground
CPRSET Pin Resistor
2.7
5.1
10
k
Sets internal CP current range, nominally 4.8 mA (CP_lsb = 600 A);
actual current can be calculated by CP_lsb = 3.06/CPRSET;
connect to ground
BYPASS Pin Capacitor
220
nF
Bypass for internal LDO regulator; necessary for LDO stability;
connect to ground
PLL CHARACTERISTICS
Table 2.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
VCO (ON-CHIP)
Frequency Range
2300
2650
MHz
VCO Gain (KVCO)
50
MHz/V
Tuning Voltage (VT)
0.5
VCP 0.5
V
VCP ≤ VS when using internal VCO; outside of this range, the CP
spurs may increase due to CP up/down mismatch
Frequency Pushing (Open-Loop)
1
MHz/V
Phase Noise at 100 kHz Offset
105
dBc/Hz
f = 2475 MHz
Phase Noise at 1 MHz Offset
124
dBc/Hz
f = 2475 MHz
REFERENCE INPUTS
Differential Mode (REFIN, REFIN)
Differential mode (can accommodate single-ended input by
ac grounding undriven input)
Input Frequency
0
250
MHz
Frequencies below about 1 MHz should be dc-coupled; be careful
to match VCM (self-bias voltage)
Input Sensitivity
250
mV p-p
PLL figure of merit (FOM) increases with increasing slew rate
the input sensitivity is sufficient for ac-coupled
LVPECL and LVDS signals
Self-Bias Voltage, REFIN
1.35
1.60
1.75
V
Self-Bias Voltage, REFIN
1.30
1.50
1.60
V
Self-bias voltage of REFIN1
Input Resistance, REFIN
4.0
4.8
5.9
k
Self-biased1
Input Resistance, REFIN
4.4
5.3
6.4
k
Self-biased1
Dual Single-Ended Mode (REF1, REF2)
Two single-ended CMOS-compatible inputs
Input Frequency (AC-Coupled)
20
250
MHz
Slew rate > 50 V/s
Input Frequency (DC-Coupled)
0
250
MHz
Slew rate > 50 V/s; CMOS levels
Input Sensitivity (AC-Coupled)
0.8
V p-p
Should not exceed VS p-p
Input Logic High
2.0
V
Input Logic Low
0.8
V
Input Current
100
+100
A
Pulse Width High/Low
1.8
ns
This value determines the allowable input duty cycle and is the
amount of time that a square wave is high/low
Input Capacitance
2
pF
Each pin, REFIN/REFIN (REF1/REF2)
PHASE/FREQUENCY DETECTOR (PFD)
PFD Input Frequency
100
MHz
Antibacklash pulse width = 1.3 ns, 2.9 ns
45
MHz
Antibacklash pulse width = 6.0 ns
Antibacklash Pulse Width
1.3
ns
Register 0x017[1:0] = 01b
2.9
ns
Register 0x017[1:0] = 00b; Register 0x017[1:0] = 11b
6.0
ns
Register 0x017[1:0] = 10b
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9518-1ABCPZ-RL7 | 功能描述:IC CLOCK GEN 6CH 2.5GHZ 48LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:2,000 系列:- 類型:PLL 時鐘發(fā)生器 PLL:帶旁路 輸入:LVCMOS，LVPECL 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:2:11 差分 - 輸入:輸出:是/無 頻率 - 最大:240MHz 除法器/乘法器:是/無 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:32-LQFP 供應(yīng)商設(shè)備封裝:32-TQFP（7x7） 包裝:帶卷 (TR) |
| AD9518-1A-PCBZ | 制造商:AD 制造商全稱:Analog Devices 功能描述:6-Output Clock Generator with Integrated 2.5 GHz VCO |
| AD9518-1BCPZ | 制造商:Analog Devices 功能描述:Clock Generator 48-Pin LFCSP EP Tray |
| AD9518-1BCPZ-REEL7 | 制造商:Analog Devices 功能描述: 制造商:Rochester Electronics LLC 功能描述: |
| AD9518-2 | 制造商:AD 制造商全稱:Analog Devices 功能描述:6-Output Clock Generator with Integrated 2.2 GHz VCO |
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