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參數資料
| 型號： | AD9517-2A/PCBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數： | 59/80頁 |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION FOR AD9517-2A |
| 設計資源： | AD9517 Eval Brd Schematics AD9517 Gerber Files AD9517-2 BOM |
| 標準包裝： | 1 |
| 主要目的： | 計時，時鐘發(fā)生器 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | AD9517-2A |
| 主要屬性： | 2 輸入，12 輸出，2.2GHz VCO |
| 次要屬性： | CMOS，LVPECL 和 LVDS 兼容 |
| 已供物品： | 板 |
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AD9517-2
Data Sheet
Rev. E | Page 62 of 80
Reg.
Addr.
(Hex)
Bits
Name
Description
0x017
[1:0]
Antibacklash
1
0
Antibacklash Pulse Width (ns)
pulse width
0
2.9 (default). This is the recommended setting; it does not normally need to be changed.
0
1
1.3. This setting may be necessary if the PFD frequency > 50 MHz.
1
0
6.0.
1
2.9.
0x018
[6:5]
Lock detect
counter
Required consecutive number of PFD cycles with edges inside lock detect window before the DLD indicates a locked
condition.
6
5
PFD Cycles to Determine Lock
0
5 (default).
0
1
16.
1
0
64.
1
255.
4
Digital lock detect
window
If the time difference of the rising edges at the inputs to the PFD is less than the lock detect window time, the digital lock
detect flag is set. The flag remains set until the time difference is greater than the loss-of-lock threshold.
0: high range (default).
1: low range.
3
Disable digital
Digital lock detect operation.
lock detect
0: normal lock detect operation (default).
1: disables lock detect.
[2:1]
VCO cal divider
VCO calibration divider. Divider used to generate the VCO calibration clock from the PLL reference clock.
2
1
VCO Calibration Clock Divider
0
2. This setting is fine for PFD frequencies < 12.5 MHz. The PFD frequency is fREF/R.
0
1
4. This setting is fine for PFD frequencies < 25 MHz.
1
0
8. This setting is fine for PFD frequencies < 50 MHz.
1
16 (default). This setting is fine for any PFD frequency but also results in the longest VCO calibration time.
0
VCO cal now
Bit used to initiate the VCO calibration. This bit must be toggled from 0b to 1b in the active registers. To initiate
calibration, use the following three steps: first, ensure that the input reference signal is present; second, set to 0b (if
not zero already), followed by an update bit (Register 0x232, Bit 0); and third, program to 1b, followed by another update
bit (Register 0x232, Bit 0). Clearing this bit discards the VCO calibration and usually results in the PLL losing lock.
The user must ensure that the holdover enable bits in Register 0x01D = 00b during VCO calibration.
0x019
[7:6]
R, A, B counters
7
6
Action
SYNC pin reset
0
Does nothing on SYNC (default).
0
1
Asynchronous reset.
1
0
Synchronous reset.
1
Does nothing on SYNC.
[5:3]
R path delay
R path delay (default = 0x00) (see Table 2).
[2:0]
N path delay
N path delay (default = 0x00) (see Table 2).
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