參數(shù)資料
型號(hào)： AD9517-2A/PCBZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 42/80頁(yè)
文件大?。?/td> 0K
描述： BOARD EVALUATION FOR AD9517-2A
設(shè)計(jì)資源： AD9517 Eval Brd Schematics
AD9517 Gerber Files
AD9517-2 BOM
標(biāo)準(zhǔn)包裝： 1
主要目的： 計(jì)時(shí)，時(shí)鐘發(fā)生器
嵌入式： 否
已用 IC / 零件： AD9517-2A
主要屬性： 2 輸入，12 輸出，2.2GHz VCO
次要屬性： CMOS，LVPECL 和 LVDS 兼容
已供物品： 板
Data Sheet
AD9517-2
Rev. E | Page 47 of 80
Calculating the Fine Delay
The following values and equations are used to calculate the
delay of the delay block.
IRAMP (A) = 200 × (Ramp Current + 1)
Number of Capacitors = Number of Bits =
0 in Ramp Capacitors + 1
Example: 101 = 1 + 1 = 2; 110 = 1 + 1 = 2; 100 = 2 + 1 = 3;
001 = 2 + 1 = 3; 111 = 0 + 1 = 1.
Delay Range (ns) = 200 × ((No. of Caps + 3)/(IRAMP)) × 1.3286
( )
(
)
6
1
10
1600
0.34
ns
4
×
+
×
+
=
RAMP
I
Caps
of
No.
I
Offset
Delay Full Scale (ns) = Delay Range + Offset
Fine Delay (ns) =
Delay Range × Delay Fraction × (1/63) + Offset
Note that only delay fraction values up to 47 decimal (101111b;
0x2F) are supported.
In no case can the fine delay exceed one-half of the output clock
period. If a delay longer than half of the clock period is attempted,
the output stops clocking.
The delay function adds some jitter that is greater than that
specified for the nondelayed output. This means that the delay
function should be used primarily for clocking digital chips,
such as FPGA, ASIC, DUC, and DDC. An output with this
delay enabled may not be suitable for clocking data converters.
The jitter is higher for long full scales because the delay block
uses a ramp and trip points to create the variable delay. A slower
ramp time produces more time jitter.
Synchronizing the Outputs—Sync Function
The AD9517 clock outputs can be synchronized to each other.
Outputs can be individually excluded from synchronization.
Synchronization consists of setting the nonexcluded outputs to
a preset set of static conditions and subsequently releasing these
outputs to continue clocking at the same instant with the preset
conditions applied. This allows for the alignment of the edges of
two or more outputs or for the spacing of edges according to the
coarse phase offset settings for two or more outputs.
Synchronization of the outputs is executed in several ways,
as follows:
By forcing the SYNC pin low and then releasing it (manual
sync).
By setting and then resetting any one of the following three
bits: the soft sync bit (Register 0x230[0]), the soft reset bit
(Register 0x000[2] [mirrored]), and the power-down
distribution reference bit (Register 0x230[1]).
By executing synchronization of the outputs as part of the
chip power-up sequence.
By forcing the RESET pin low and then releasing it (chip
reset).
By forcing the PD pin low and then releasing it (chip power-
down).
Following completion of a VCO calibration. An internal
SYNC signal is automatically asserted at the beginning of
a VCO calibration and then released upon its completion.
The most common way to execute the sync function is to use
the SYNC pin to do a manual synchronization of the outputs.
This requires a low-going signal on the SYNC pin, which is held
low and then released when synchronization is desired. The
timing of the sync operation is shown in Figure 57 (using VCO
divider) and Figure 58 (VCO divider not used). There is an
uncertainty of up to one cycle of the clock at the input to the
channel divider due to the asynchronous nature of the SYNC
signal with respect to the clock edges inside the AD9517. The
delay from the SYNC rising edge to the beginning of synchronized
output clocking is between 14 and 15 cycles of clock at the
channel divider input, plus either one cycle of the VCO divider
input (see Figure 57), or one cycle of the channel divider input
(see Figure 58), depending on whether the VCO divider is used.
Cycles are counted from the rising edge of the signal.
Another common way to execute the sync function is by setting
and resetting the soft sync bit at Register 0x230[0] (see Table 53
through Table 62 for details). Both the setting and resetting
of the soft sync bit require an update all registers operation
(Register 0x232[0] = 1) to take effect.
相關(guān)PDF資料
PDF描述
VI-J00-EZ-S CONVERTER MOD DC/DC 5V 25W
ILC0402ER15NK INDUCTOR CER 15NH 0402
SP1210R-473K INDUCTOR PWR SHIELDED 47.0UH SMD
MCP121T-300E/TT IC SUPERVISOR 2.93V LOW SOT-23B
AD9517-4A/PCBZ BOARD EVALUATION FOR AD9517-4A
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD9517-2BCPZ 制造商:Analog Devices 功能描述:Clock Generator 48-Pin LFCSP EP Tray
AD9517-2BCPZ-REEL7 制造商:Analog Devices 功能描述:
AD9517-2BCPZ-TR 制造商:Analog Devices 功能描述:OUPUT CLOCK GENERATOR WITH 2.2HZ VCO - Tape and Reel
AD9517-3 制造商:AD 制造商全稱:Analog Devices 功能描述:12-Output Clock Generator with Integrated 2.0 GHz VCO
AD9517-3A/PCBZ 功能描述:BOARD EVALUATION FOR AD9517-3A RoHS:是 類別:編程器，開(kāi)發(fā)系統(tǒng) >> 評(píng)估演示板和套件 系列:- 標(biāo)準(zhǔn)包裝:1 系列:PSoC® 主要目的:電源管理，熱管理 嵌入式:- 已用 IC / 零件:- 主要屬性:- 次要屬性:- 已供物品:板，CD，電源
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*