參數(shù)資料
型號: AD9517-1ABCPZ
廠商: Analog Devices Inc
文件頁數(shù): 6/80頁
文件大小: 0K
描述: IC CLOCK GEN 2.5GHZ VCO 48LFCSP
標(biāo)準(zhǔn)包裝: 1
類型: 時鐘發(fā)生器,扇出配送
PLL:
輸入: CMOS,LVDS,LVPECL
輸出: CMOS,LVDS,LVPECL
電路數(shù): 1
比率 - 輸入:輸出: 1:12
差分 - 輸入:輸出: 是/是
頻率 - 最大: 2.65GHz
除法器/乘法器: 是/無
電源電壓: 3.135 V ~ 3.465 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 48-LFCSP
供應(yīng)商設(shè)備封裝: 48-LFCSP-VQ(7x7)
包裝: 托盤
AD9517-1
Data Sheet
Rev. E | Page 14 of 80
PD, SYNC, AND RESET PINS
Table 15.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
INPUT CHARACTERISTICS
These pins each have a 30 k internal pull-up
resistor
Logic 1 Voltage
2.0
V
Logic 0 Voltage
0.8
V
Logic 1 Current
1
A
Logic 0 Current
110
A
Capacitance
2
pF
RESET TIMING
Pulse Width Low
50
ns
SYNC TIMING
Pulse Width Low
1.5
High speed
clock cycles
High speed clock is CLK input signal
LD, STATUS, AND REFMON PINS
Table 16.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
OUTPUT CHARACTERISTICS
When selected as a digital output (CMOS); there
are other modes in which these pins are not CMOS
digital outputs; see Table 54, Register 0x017,
Register 0x01A, and Register 0x01B
Output Voltage High (VOH)
2.7
V
Output Voltage Low (VOL)
0.4
V
MAXIMUM TOGGLE RATE
100
MHz
Applies when mux is set to any divider or counter
output or PFD up/down pulse; also applies in
analog lock detect mode; usually debug mode
only; beware that spurs may couple to output
when any of these pins are toggling
ANALOG LOCK DETECT
Capacitance
3
pF
On-chip capacitance; used to calculate RC time
constant for analog lock detect readback; use a
pull-up resistor
REF1, REF2, AND VCO FREQUENCY STATUS MONITOR
Normal Range
1.02
MHz
Frequency above which the monitor always
indicates the presence of the reference
Extended Range (REF1 and REF2 Only)
8
kHz
Frequency above which the monitor always
indicates the presence of the reference
LD PIN COMPARATOR
Trip Point
1.6
V
Hysteresis
260
mV
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