- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄9158 > AD9517-1ABCPZ (Analog Devices Inc)IC CLOCK GEN 2.5GHZ VCO 48LFCSP PDF資料下載
參數(shù)資料
| 型號： | AD9517-1ABCPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 28/80頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK GEN 2.5GHZ VCO 48LFCSP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 時(shí)鐘發(fā)生器，扇出配送 |
| PLL： | 是 |
| 輸入： | CMOS，LVDS，LVPECL |
| 輸出： | CMOS，LVDS，LVPECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:12 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 2.65GHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-LFCSP |
| 供應(yīng)商設(shè)備封裝： | 48-LFCSP-VQ（7x7） |
| 包裝： | 托盤 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁當(dāng)前第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁
AD9517-1
Data Sheet
Rev. E | Page 34 of 80
Charge Pump (CP)
The charge pump is controlled by the PFD. The PFD monitors
the phase and frequency relationship between its two inputs
and tells the CP to pump up or pump down to charge or
discharge the integrating node (part of the loop filter). The
integrated and filtered CP current is transformed into a voltage
that drives the tuning node of the internal VCO through the LF
pin (or the tuning pin of an external VCO) to move the VCO
frequency up or down. The CP can be set (Register 0x010[6:4])
for high impedance (allows holdover operation), for normal
operation (attempts to lock the PLL loop), for pump up, or for
pump down (test modes). The CP current is programmable in
eight steps from (nominally) 600 A to 4.8 mA. The exact value
of the CP current LSB is set by the CPRSET resistor, which is
nominally 5.1 k. If the value of the resistor that is connected
to the CP_RSET pin is doubled, the resulting charge pump current
range becomes 300 A to 2.4 mA.
On-Chip VCO
The AD9517 includes an on-chip VCO covering the frequency
range shown in Table 2. The calibration procedure ensures that
the VCO operating voltage is centered for the desired VCO
frequency. The VCO must be calibrated when the VCO loop
is first set up, as well as any time the nominal VCO frequency
changes. However, once the VCO is calibrated, the VCO has
sufficient operating range to stay locked over temperature and
voltage extremes without needing additional calibration. See the
VCO Calibration section for additional information.
The on-chip VCO is powered by an on-chip, low dropout
(LDO), linear voltage regulator. The LDO provides some
isolation of the VCO from variations in the power supply
voltage level. The BYPASS pin should be connected to ground
by a 220 nF capacitor to ensure stability. This LDO employs the
same technology used in the anyCAP line of regulators from
Analog Devices, Inc., making it insensitive to the type of
capacitor used. Driving an external load from the BYPASS pin
is not supported.
Note that the reference input signal must be present and the
VCO divider must not be static during VCO calibration.
PLL External Loop Filter
When using the internal VCO, the external loop filter should be
referenced to the BYPASS pin for optimal noise and spurious
performance. An example of an external loop filter for a PLL
that uses the internal VCO is shown in Figure 47. The third-
order design shown in Figure 47 usually offers best performance.
A loop filter must be calculated for each desired PLL configuration.
The values of the components depend upon the VCO frequency,
the KVCO, the PFD frequency, the CP current, the desired loop
bandwidth, and the desired phase margin. The loop filter affects
the phase noise, loop settling time, and loop stability. A basic
knowledge of PLL theory is helpful for understanding loop filter
design. ADIsimCLK can help with the calculation of a loop
filter according to the application requirements.
When using an external VCO, the external loop filter should
be referenced to ground. See Figure 48 for an example of an
external loop filter for a PLL using an external VCO.
LF
VCO
CHARGE
PUMP
CP
BYPASS
C1
C2
C3
R1
31pF
R2
CBP = 220nF
AD9517-1
06425-
065
Figure 47. Example of External Loop Filter for a PLL Using the Internal VCO
CLK/CLK
EXTERNAL
VCO/VCXO
CHARGE
PUMP
CP
C1
C2
C3
R1
R2
AD9517-1
06425-
265
Figure 48. Example of External Loop Filter for a PLL Using an External VCO
PLL Reference Inputs
The AD9517 features a flexible PLL reference input circuit that
allows either a fully differential input or two separate single-
ended inputs. The input frequency range for the reference
inputs is specified in Table 2. Both the differential and
the single-ended inputs are self-biased, allowing for easy
ac coupling of input signals.
The differential input and the single-ended inputs share the two
pins, REFIN and REFIN (REF1 and REF2, respectively). The
desired reference input type is selected and controlled by Register
0x01C (see Table 52 and Table 54).
When the differential reference input is selected, the self-bias
level of the two sides is offset slightly (~100 mV, see Table 2) to
prevent chattering of the input buffer when the reference is slow
or missing. This increases the voltage swing that is required of
the driver and overcomes the offset. The differential reference
input can be driven by either ac-coupled LVDS or ac-coupled
LVPECL signals.
The single-ended inputs can be driven by either a dc-coupled
CMOS level signal or an ac-coupled sine wave or square wave.
Each single-ended input can be independently powered down
when not needed to increase isolation and reduce power. Either
a differential or a single-ended reference must be specifically
enabled. All PLL reference inputs are off by default.
The differential reference input is powered down whenever the
PLL is powered down or when the differential reference input is
not selected. The single-ended buffers power down when the
PLL is powered down and when their individual power-down
registers are set. When the differential mode is selected, the
single-ended inputs are powered down.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| V110A48H300BL2 | CONVERTER MOD DC/DC 48V 300W |
| AD9511BCPZ | IC CLOCK DIST 5OUT PLL 48LFCSP |
| V110A48H300BL | CONVERTER MOD DC/DC 48V 300W |
| VI-B60-MV | CONVERTER MOD DC/DC 5V 150W |
| AD9518-2ABCPZ | IC CLOCK GEN 6CH 2.2GHZ 48LFCSP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9517-1ABCPZ-RL7 | 功能描述:IC CLOCK GEN 2.5GHZ VCO 48LFCSP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:2,000 系列:- 類型:PLL 時(shí)鐘發(fā)生器 PLL:帶旁路 輸入:LVCMOS，LVPECL 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:2:11 差分 - 輸入:輸出:是/無 頻率 - 最大:240MHz 除法器/乘法器:是/無 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:32-LQFP 供應(yīng)商設(shè)備封裝:32-TQFP（7x7） 包裝:帶卷 (TR) |
| AD9517-1BCPZ | 制造商:Analog Devices 功能描述:Clock Generator 48-Pin LFCSP EP Tray 制造商:Analog Devices 功能描述:CLOCK GEN 12-OUTPUT VCO LFCSP-48 |
| AD9517-1BCPZ-REEL | 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述: |
| AD9517-1BCPZ-REEL7 | 制造商:Analog Devices 功能描述: |
| AD9517-2A/PCBZ | 功能描述:BOARD EVALUATION FOR AD9517-2A RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 主要目的:電信，線路接口單元（LIU） 嵌入式:- 已用 IC / 零件:IDT82V2081 主要屬性:T1/J1/E1 LIU 次要屬性:- 已供物品:板，電源，線纜，CD 其它名稱:82EBV2081 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。