參數(shù)資料
型號： AD9517-0ABCPZ-RL7
廠商： Analog Devices Inc
文件頁數(shù)： 40/80頁
文件大?。?/td> 0K
描述： IC CLOCK GEN 2.8GHZ VCO 48LFCSP
標(biāo)準(zhǔn)包裝： 750
類型： 時鐘發(fā)生器，扇出配送
PLL： 是
輸入： CMOS，LVDS，LVPECL
輸出： LVDS，LVPECL
電路數(shù)： 1
比率 - 輸入:輸出： 1:12
差分 - 輸入:輸出： 是/是
頻率 - 最大： 2.95GHz
除法器/乘法器： 是/無
電源電壓： 3.135 V ~ 3.465 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 48-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 48-LFCSP-VQ（7x7）
包裝： 帶卷 (TR)
Data Sheet
AD9517-0
Rev. E | Page 45 of 80
Duty Cycle and Duty-Cycle Correction (Divider 2 and
Divider 3)
The same duty cycle and DCC considerations apply to Divider 2
and Divider 3 as to Divider 0 and Divider 1 (see the Duty Cycle
and Duty-Cycle Correction (0, 1) section); however, with these
channel dividers, the number of possible configurations is even
more complex.
Duty-cycle correction on Divider 2 and Divider 3 requires the
following channel divider conditions:
An even DX.Y must be set as MX.Y = NX.Y (low cycles = high
cycles).
An odd DX.Y must be set as MX.Y = NX.Y + 1 (the number of
low cycles must be one greater than the number of high
cycles).
If only one divider is bypassed, it must be the second
divider, X.2.
If only one divider has an even divide-by, it must be the
second divider, X.2.
The possibilities for the duty cycle of the output clock from
Divider 2 and Divider 3 are shown in Table 40 through
Table 40. Divider 2 and Divider 3 Duty Cycle; VCO Divider
Used; Duty Cycle Correction Off (DCCOFF = 1)
VCO
Divider
DX.1
DX.2
Output
Duty Cycle
NX.1 + MX.1 + 2
NX.2 + MX.2 + 2
Even
1
50%
Odd = 3
1
33.3%
Odd = 5
1
40%
Even
Even, odd
1
(NX.1 + 1)/
(NX.1 + MX.1 + 2)
Odd
Even, odd
1
(NX.1 + 1)/
(NX.1 + MX.1 + 2)
Even
Even, odd
(NX.2 + 1)/
(NX.2 + MX.2 + 2)
Odd
Even, odd
(NX.2 + 1)/
(NX.2 + MX.2 + 2)
Table 41. Divider 2 and Divider 3 Duty Cycle; VCO Divider
Not Used; Duty Cycle Correction Off (DCCOFF = 1)
Input Clock
Duty Cycle
DX.1
DX.2
Output
Duty Cycle
NX.1 + MX.1 + 2
NX.2 + MX.2 + 2
50%
1
50%
X%
1
X%
50%
Even, odd
1
(NX.1 + 1)/
(NX.1 + MX.1 + 2)
X%
Even, odd
1
(NX.1 + 1)/
(NX.1 + MX.1 + 2)
50%
Even, odd
(NX.2 + 1)/
(NX.2 + MX.2 + 2)
X%
Even, odd
(NX.2 + 1)/
(NX.2 + MX.2 + 2)
Table 42. Divider 2 and Divider 3 Duty Cycle; VCO Divider
Used; Duty Cycle Correction Is On (DCCOFF = 0); VCO
Divider Input Duty Cycle = 50%
VCO
Divider
DX.1
DX.2
Output
Duty Cycle
NX.1 + MX.1 + 2
NX.2 + MX.2 + 2
Even
1
50%
Odd
1
50%
Even
Even (NX.1 = MX.1)
1
50%
Odd
Even (NX.1 = MX.1)
1
50%
Even
Odd (MX.1 = NX.1 + 1)
1
50%
Odd
Odd (MX.1 = NX.1 + 1)
1
50%
Even
Even (NX.1 = MX.1)
Even (NX.2 = MX.2)
50%
Odd
Even (NX.1 = MX.1)
Even (NX.2 = MX.2)
50%
Even
Odd (MX.1 = NX.1 + 1)
Even (NX.2 = MX.2)
50%
Odd
Odd (MX.1 = NX.1 + 1)
Even (NX.2 = MX.2)
50%
Even
Odd (MX.1 = NX.1 + 1)
Odd (MX.2 = NX.2 + 1)
50%
Odd
Odd (MX.1 = NX.1 + 1)
Odd (MX.2 = NX.2 + 1)
50%
Table 43. Divider 2 and Divider 3 Duty Cycle; VCO Divider
Used; Duty Cycle Correction On (DCCOFF = 0); VCO
Divider Input Duty Cycle = X%
VCO
Divider
DX.1
DX.2
Output
Duty Cycle
NX.1 + MX.1 + 2
NX.2 + MX.2 + 2
Even
1
50%
Odd = 3
1
(1 + X%)/3
Odd = 5
1
(2 + X%)/5
Even
(NX.1 = MX.1)
1
50%
Odd
Even
(NX.1 = MX.1)
1
50%
Even
Odd
(MX.1 = NX.1 + 1)
1
50%
Odd = 3
Odd
(MX.1 = NX.1 + 1)
1
(3NX.1 + 4 + X%)/
(6NX.1 + 9)
Odd = 5
Odd
(MX.1 = NX.1 + 1)
1
(5NX.1 + 7 + X%)/
(10NX.1 + 15)
Even
(NX.1 = MX.1)
Even
(NX.2 = MX.2)
50%
Odd
Even
(NX.1 = MX.1)
Even
(NX.2 = MX.2)
50%
Even
Odd
(MX.1 = NX.1 + 1)
Even
(NX.2 = MX.2)
50%
Odd
(MX.1 = NX.1 + 1)
Even
(NX.2 = MX.2)
50%
Even
Odd
(MX.1 = NX.1 + 1)
Odd
(MX.2 = NX.2 + 1)
50%
Odd = 3
Odd
(MX.1 = NX.1 + 1)
Odd
(MX.2 = NX.2 + 1)
(6NX.1NX.2 + 9NX.1 +
9NX.2 + 13 + X%)/
(3(2NX.1 + 3)
(2NX.2 + 3))
Odd = 5
Odd
(MX.1 = NX.1 + 1)
Odd
(MX.2 = NX.2 + 1)
(10NX.1NX.2+ 15NX.1 +
15NX.2 + 22 + X%)/
(5(2 NX.1 + 3)
(2 NX.2 + 3))
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參數(shù)描述
AD9517-0BCPZ 制造商:Analog Devices 功能描述:
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