參數(shù)資料
型號: AD9511BCPZ
廠商: Analog Devices Inc
文件頁數(shù): 4/60頁
文件大小: 0K
描述: IC CLOCK DIST 5OUT PLL 48LFCSP
標(biāo)準(zhǔn)包裝: 1
類型: 扇出緩沖器(分配),除法器
PLL:
輸入: 時鐘
輸出: CMOS,LVDS,LVPECL
電路數(shù): 1
比率 - 輸入:輸出: 2:5
差分 - 輸入:輸出: 是/是
頻率 - 最大: 1.2GHz
除法器/乘法器: 是/無
電源電壓: 3.135 V ~ 3.465 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 48-VFQFN 裸露焊盤,CSP
供應(yīng)商設(shè)備封裝: 48-LFCSP-VQ(7x7)
包裝: 托盤
產(chǎn)品目錄頁面: 776 (CN2011-ZH PDF)
AD9511
Rev. A | Page 12 of 60
CLOCK OUTPUT ADDITIVE TIME JITTER
Table 6.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
LVPECL OUTPUT ADDITIVE TIME JITTER
Distribution Section only; does not
include PLL or external VCO/VCXO
CLK1 = 622.08 MHz
40
fs rms
BW = 12 kHz 20 MHz (OC-12)
Any LVPECL (OUT0 to OUT2) = 622.08 MHz
Divide Ratio = 1
CLK1 = 622.08 MHz
55
fs rms
BW = 12 kHz 20 MHz (OC-3)
Any LVPECL (OUT0 to OUT2) = 155.52 MHz
Divide Ratio = 4
CLK1 = 400 MHz
215
fs rms
Calculated from SNR of ADC method;
FC = 100 MHz with AIN = 170 MHz
Any LVPECL (OUT0 to OUT2) = 100 MHz
Divide Ratio = 4
CLK1 = 400 MHz
215
fs rms
Calculated from SNR of ADC method;
FC = 100 MHz with AIN = 170 MHz
Any LVPECL (OUT0 to OUT2) = 100 MHz
Divide Ratio = 4
Other LVPECL = 100 MHz
Interferer(s)
Both LVDS (OUT3, OUT4) = 100 MHz
Interferer(s)
CLK1 = 400 MHz
222
fs rms
Calculated from SNR of ADC method;
FC = 100 MHz with AIN = 170 MHz
Any LVPECL (OUT0 to OUT2) = 100 MHz
Divide Ratio = 4
Other LVPECL = 50 MHz
Interferer(s)
Both LVDS (OUT3, OUT4) = 50 MHz
Interferer(s)
CLK1 = 400 MHz
225
fs rms
Calculated from SNR of ADC method;
FC = 100 MHz with AIN = 170 MHz
Any LVPECL (OUT0 to OUT2) = 100 MHz
Divide Ratio = 4
Other LVPECL = 50 MHz
Interferer(s)
Both CMOS (OUT3, OUT4) = 50 MHz (B Outputs Off)
Interferer(s)
CLK1 = 400 MHz
225
fs rms
Calculated from SNR of ADC method;
FC = 100 MHz with AIN = 170 MHz
Any LVPECL (OUT0 to OUT2) = 100 MHz
Divide Ratio = 4
Other LVPECL = 50 MHz
Interferer(s)
Both CMOS (OUT3, OUT4) = 50 MHz (B Outputs On)
Interferer(s)
LVDS OUTPUT ADDITIVE TIME JITTER
Distribution Section only; does not
include PLL or external VCO/VCXO
CLK1 = 400 MHz
264
fs rms
Calculated from SNR of ADC method;
FC = 100 MHz with AIN = 170 MHz
LVDS (OUT3) = 100 MHz
Divide Ratio = 4
CLK1 = 400 MHz
319
fs rms
Calculated from SNR of ADC method;
FC = 100 MHz with AIN = 170 MHz
LVDS (OUT4) = 100 MHz
Divide Ratio = 4
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