Typical (typ) is given for VS = 3.3 V ± 5%;" />
參數(shù)資料
型號: AD9511BCPZ
廠商: Analog Devices Inc
文件頁數(shù): 34/60頁
文件大?。?/td> 0K
描述: IC CLOCK DIST 5OUT PLL 48LFCSP
標(biāo)準(zhǔn)包裝: 1
類型: 扇出緩沖器(分配),除法器
PLL:
輸入: 時鐘
輸出: CMOS,LVDS,LVPECL
電路數(shù): 1
比率 - 輸入:輸出: 2:5
差分 - 輸入:輸出: 是/是
頻率 - 最大: 1.2GHz
除法器/乘法器: 是/無
電源電壓: 3.135 V ~ 3.465 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 48-VFQFN 裸露焊盤,CSP
供應(yīng)商設(shè)備封裝: 48-LFCSP-VQ(7x7)
包裝: 托盤
產(chǎn)品目錄頁面: 776 (CN2011-ZH PDF)
AD9511
Rev. A | Page 4 of 60
SPECIFICATIONS
Typical (typ) is given for VS = 3.3 V ± 5%; VS ≤ VCPS ≤ 5.5 V, TA = 25°C, RSET = 4.12 kΩ, CPRSET = 5.1 kΩ, unless otherwise noted.
Minimum (min) and maximum (max) values are given over full VS and TA (40°C to +85°C) variation.
PLL CHARACTERISTICS
Table 1.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
REFERENCE INPUTS (REFIN)
Input Frequency
0
250
MHz
Input Sensitivity
150
mV p-p
Self-Bias Voltage, REFIN
1.45
1.60
1.75
V
Self-bias voltage of REFIN1.
Self-Bias Voltage, REFINB
1.40
1.50
1.60
V
Self-bias voltage of REFINB1.
Input Resistance, REFIN
4.0
4.9
5.8
Self-biased1.
Input Resistance, REFINB
4.5
5.4
6.3
Self-biased1.
Input Capacitance
2
pF
PHASE/FREQUENCY DETECTOR (PFD)
PFD Input Frequency
100
MHz
Antibacklash pulse width 0Dh<1:0> = 00b.
PFD Input Frequency
100
MHz
Antibacklash pulse width 0Dh<1:0> = 01b.
PFD Input Frequency
45
MHz
Antibacklash pulse width 0Dh<1:0> = 10b.
Antibacklash Pulse Width
1.3
ns
0Dh<1:0> = 00b. (This is the default setting.)
Antibacklash Pulse Width
2.9
ns
0Dh<1:0> = 01b.
Antibacklash Pulse Width
6.0
ns
0Dh<1:0> = 10b.
CHARGE PUMP (CP)
ICP Sink/Source
Programmable.
High Value
4.8
mA
Low Value
0.60
mA
With CPRSET = 5.1 kΩ.
Absolute Accuracy
2.5
%
VCP = VCPS/2.
CPRSET Range
2.7/10
ICP Three-State Leakage
1
nA
Sink-and-Source Current Matching
2
%
0.5 < VCP < VCPS 0.5 V.
ICP vs. VCP
1.5
%
0.5 < VCP < VCPS 0.5 V.
ICP vs. Temperature
2
%
VCP = VCPS/2 V.
RF CHARACTERISTICS (CLK2)2
Input Frequency
1.6
GHz
Frequencies > 1200 MHz (LVPECL) or
800 MHz (LVDS) require a minimum
divide-by-2 (see the Distribution Section).
Input Sensitivity
150
mV p-p
Input Common-Mode Voltage, VCM
1.5
1.6
1.7
V
Self-biased; enables ac coupling.
Input Common-Mode Range, VCMR
1.3
1.8
V
With 200 mV p-p signal applied.
Input Sensitivity, Single-Ended
150
mV p-p
CLK2 ac-coupled; CLK2B capacitively
bypassed to RF ground.
Input Resistance
4.0
4.8
5.6
Self-biased.
Input Capacitance
2
pF
CLK2 VS. REFIN DELAY
500
ps
Difference at PFD.
PRESCALER (PART OF N DIVIDER)
section.
Prescaler Input Frequency
P = 2 DM (2/3)
600
MHz
P = 4 DM (4/5)
1000
MHz
P = 8 DM (8/9)
1600
MHz
P = 16 DM (16/17)
1600
MHz
P = 32 DM (32/33)
1600
MHz
CLK2 Input Frequency for PLL
300
MHz
A, B counter input frequency.
相關(guān)PDF資料
PDF描述
V110A48H300BL CONVERTER MOD DC/DC 48V 300W
VI-B60-MV CONVERTER MOD DC/DC 5V 150W
AD9518-2ABCPZ IC CLOCK GEN 6CH 2.2GHZ 48LFCSP
VI-B4Z-MV-B1 CONVERTER MOD DC/DC 2V 60W
VI-B3D-MW-B1 CONVERTER MOD DC/DC 85V 100W
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD9511BCPZ-REEL 制造商:AD 制造商全稱:Analog Devices 功能描述:1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Five Outputs
AD9511BCPZ-REEL7 功能描述:IC CLOCK DIST 5OUT PLL 48LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器,PLL,頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:2,000 系列:- 類型:PLL 時鐘發(fā)生器 PLL:帶旁路 輸入:LVCMOS,LVPECL 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:2:11 差分 - 輸入:輸出:是/無 頻率 - 最大:240MHz 除法器/乘法器:是/無 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:32-LQFP 供應(yīng)商設(shè)備封裝:32-TQFP(7x7) 包裝:帶卷 (TR)
AD9511-VCO/PCB 制造商:Analog Devices 功能描述:EVAL BD FOR AD9511 1.2 GHZ CLOCK DISTRIBUTION IC, PLL CORE,D - Bulk
AD9512 制造商:AD 制造商全稱:Analog Devices 功能描述:800 MHz Clock Distribution IC,1.5 GHz Inputs, Dividers, Delay Adjust, Five Outputs
AD9512/PCB 制造商:Analog Devices 功能描述:Evaluation Kit For 1.2 GHZ Clock Distribution IC, 1.6 GHZ Inputs, Dividers, Delay Adjust, Five Outputs 制造商:Analog Devices 功能描述:EVAL KIT FOR 1.2 GHZ CLOCK DISTRIBUTION IC, 1.6 GHZ INPUTS, - Bulk