參數(shù)資料
型號(hào)： AD9445BSVZ-125
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 21/40頁(yè)
文件大?。?/td> 0K
描述： IC ADC 14BIT 125MSPS 100-TQFP
設(shè)計(jì)資源： Using AD8376 to Drive Wide Bandwidth ADCs for High IF AC-Coupled Appls (CN0002)
Using AD8352 as an Ultralow Distortion Differential RF/IF Front End for High Speed ADCs (CN0046)
Using ADL5562 Differential Amplifier to Drive Wide Bandwidth ADCs for High IF AC-Coupled Appls (CN0110)
標(biāo)準(zhǔn)包裝： 1
位數(shù)： 14
采樣率（每秒）： 125M
數(shù)據(jù)接口： 并聯(lián)
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 2.6W
電壓電源： 單電源
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 100-TQFP 裸露焊盤
供應(yīng)商設(shè)備封裝： 100-TQFP-EP（14x14）
包裝： 托盤
輸入數(shù)目和類型： 1 個(gè)差分，單極
AD9445
Rev. 0 | Page 28 of 40
OPERATIONAL MODE SELECTION
Data Format Select
The data format select (DFS) pin of the AD9445 determines
the coding format of the output data. This pin is 3.3 V CMOS-
compatible, with logic high (or AVDD1, 3.3 V) selecting twos
complement and DFS logic low (AGND) selecting offset binary
format. Table 10 summarizes the output coding.
Output Mode Select
The OUPUT MODE pin controls the logic compatibility, as well
as the pinout of the digital outputs. This pin is a CMOS-compatible
input. With OUTPUT MODE = 0 (AGND), the AD9445 outputs
are CMOS compatible, and the pin assignment for the device is
as defined in Table 8. With OUTPUT MODE = 1 (AVDD1, 3.3
V), the AD9445 outputs are LVDS compatible, and the pin
assignment for the device is as defined in Table 7.
Duty Cycle Stabilizer
The DCS circuit is controlled by the DCS MODE pin; a CMOS
logic low (AGND) on DCS MODE enables the DCS, and logic
high (AVDD1, 3.3 V) disables the controller.
RF ENABLE
The RF ENABLE pin is a CMOS-compatible control pin that
optimizes the configuration of the AD9445 analog front end.
The crossover analog input frequency for determining the
RF ENABLE connection differs for the 105 MSPS and 125 MSPS
speed grades. For the 125 MSPS speed grade, connecting the
RF ENABLE to AGND optimizes SFDR performance for appli-
cations with analog input frequencies <210 MHz. For applications
with analog inputs >210 MHz, this pin should be connected to
AVDD1 for optimum SFDR performance. Connecting this pin to
AVDD1 reconfigures the ADC, thereby improving high IF and RF
spurious performance. Operating in this mode increases power dis-
sipation from AVDD2 by 150 mW to 200 mW. For the 105 MSPS
speed grade, connecting RF ENABLE to AGND optimizes SFDR
performance for applications with analog input frequencies
<230 MHz. For applications with analog inputs >230 MHz, this
pin should be connected to AVDD1 to optimize performance.
Table 10. Digital Output Coding
Code
VIN+ VIN
Input Span = 3.2 V p-p (V)
VIN+ VIN
Input Span = 2 V p-p (V)
Digital Output
Offset Binary (D13D0)
Digital Output
Twos Complement (D13D0)
16,383
+1.600
+1.000
11 1111 1111 1111
01 1111 1111 1111
8192
0
10 0000 0000 0000
00 0000 0000 0000
8191
0.000195
0.000122
01 1111 1111 1111
11 1111 1111 1111
0
1.60
1.00
00 0000 0000 0000
10 0000 0000 0000
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