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參數(shù)資料
| 型號： | AD9445BSVZ-125 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 17/40頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 14BIT 125MSPS 100-TQFP |
| 設(shè)計資源： | Using AD8376 to Drive Wide Bandwidth ADCs for High IF AC-Coupled Appls (CN0002) Using AD8352 as an Ultralow Distortion Differential RF/IF Front End for High Speed ADCs (CN0046) Using ADL5562 Differential Amplifier to Drive Wide Bandwidth ADCs for High IF AC-Coupled Appls (CN0110) |
| 標準包裝： | 1 |
| 位數(shù)： | 14 |
| 采樣率（每秒）： | 125M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 2.6W |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-TQFP 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 100-TQFP-EP（14x14） |
| 包裝： | 托盤 |
| 輸入數(shù)目和類型： | 1 個差分，單極 |
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AD9445
Rev. 0 | Page 24 of 40
THEORY OF OPERATION
The AD9445 architecture is optimized for high speed and ease
of use. The analog inputs drive an integrated, high bandwidth
track-and-hold circuit that samples the signal prior to quantization
by the 14-bit pipeline ADC core. The device includes an on-board
reference and input logic that accepts TTL, CMOS, or LVPECL
levels. The digital output logic levels are user selectable as standard
3 V CMOS or LVDS (ANSI-644 compatible) via the OUTPUT
MODE pin.
ANALOG INPUT AND REFERENCE OVERVIEW
A stable and accurate 0.5 V band gap voltage reference is built
into the AD9445. The input range can be adjusted by varying
the reference voltage applied to the AD9445, using either the
internal reference or an externally applied reference voltage.
The input span of the ADC tracks reference voltage changes
linearly.
Internal Reference Connection
A comparator within the AD9445 detects the potential at the
SENSE pin and configures the reference into three possible states,
which are summarized in Table 9. If SENSE is grounded, the
reference amplifier switch is connected to the internal resistor
divider (see Figure 59), setting VREF to ~1.0 V. Connecting the
SENSE pin to VREF switches the reference amplifier output to
the SENSE pin, completing the loop and providing a ~1.0 V
reference output. If a resistor divider is connected as shown in
Figure 60, the switch again sets to the SENSE pin. This puts the
reference amplifier in a noninverting mode with the VREF
output defined as
+
×
=
R1
R2
V
VREF
1
5
.
0
In all reference configurations, REFT and REFB drive the
analog-to-digital conversion core and establish its input span.
The input range of the ADC always equals twice the voltage at
the reference pin for either an internal or an external reference.
Internal Reference Trim
The internal reference voltage is trimmed during the production
test to adjust the gain (analog input voltage range) of the AD9445.
Therefore, there is little advantage to the user supplying an external
voltage reference to the AD9445. The gain trim is performed
with the AD9445 input range set to 2.0 V p-p nominal (SENSE
connected to AGND). Because of this trim and the maximum ac
performance provided by the 2.0 V p-p analog input range, there
is little benefit to using analog input ranges <2 V p-p. Users are
cautioned that the differential nonlinearity of the ADC varies
with the reference voltage. Configurations that use <2.0 V p-p
may exhibit missing codes and, therefore, degraded noise and
distortion performance.
10
μF
+
0.1
μF
VREF
SENSE
0.5V
AD9445
VIN–
VIN+
REFT
0.1
μF
0.1
μF
10
μF
0.1
μF
REFB
SELECT
LOGIC
ADC
CORE
+
05489-054
Figure 59. Internal Reference Configuration
05489-055
10
μF
+
0.1
μF
VREF
SENSE
R2
R1
0.5V
AD9445
VIN–
VIN+
REFT
0.1
μF
0.1
μF
10
μF
0.1
μF
REFB
SELECT
LOGIC
ADC
CORE
+
Figure 60. Programmable Reference Configuration
Table 9. Reference Configuration Summary
Selected Mode
SENSE Voltage
Resulting VREF (V)
Resulting Differential Span (V p-p)
External Reference
AVDD1
N/A
2 × external reference
Programmable Reference
0.2 V to VREF
+
×
R1
R2
1
0.5
(See Figure 60)
2 × VREF
Internal Fixed Reference
AGND to 0.2 V
1.0
2.0
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