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參數(shù)資料
| 型號： | AD9410BSVZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 9/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 10BIT 210MSPS 80-TQFP |
| 標準包裝： | 1 |
| 位數(shù)： | 10 |
| 采樣率（每秒）： | 210M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 2.4W |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 80-TQFP 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 80-TQFP-EP（14x14） |
| 包裝： | 托盤 |
| 輸入數(shù)目和類型： | 1 個差分，單極 |
AD9410
Rev. A | Page 17 of 20
VOLTAGE REFERENCE
A stable and accurate 2.5 V voltage reference is built into the
AD9410 (VREFOUT). The input range can be adjusted by varying
the reference voltage. No appreciable degradation in
performance occurs when the reference is adjusted ±5%. The
full-scale range of the ADC tracks reference voltage changes
linearly within the ±5% tolerance.
TIMING
The AD9410 provides latched data outputs, with six pipeline
delays in interleaved mode (see Figure 2). In parallel mode, the
Port A has one additional cycle of latency added on-chip to line
up transitions at the data ports, resulting in a latency of seven
cycles for the Port A. The length of the output data lines and
loads placed on them should be minimized to reduce transients
within the AD9410; these transients can detract from the
dynamic performance of the converter.
The minimum guaranteed conversion rate of the AD9410 is
100 MSPS. At internal clock rates below 100 MSPS, dynamic
performance may degrade. Note that lower effective sampling
rates can be obtained simply by sampling just one output port—
decimating the output by two. Lower sampling frequencies can
also be accommodated by restricting the duty cycle of the clock
such that the clock high pulse width is a maximum of 5 ns.
DATA SYNC (DS)
The data sync input, DS, can be used in applications requiring
that a given sample appear at a specific output Port A or Port B.
When DS is held high, the ADC data outputs and clock do not
switch and are held static. Synchronization is accomplished by
the assertion (falling edge) of DS, within the timing constraints
tSDS and tHDS relative to an clock rising edge. (On initial
synchronization, tHDS is not relevant.) If DS falls within the
required setup time (tSDS) before a given clock rising edge N, the
analog value at that point is digitized and available at Port B six
cycles later (interleaved mode). The next sample, N+1, is
sampled by the next rising clock edge and available at Port A six
cycles after that clock edge (interleaved mode). In dual parallel
mode, Port A has a seven cycle latency, and Port B has a six
cycle latency, but data is available at the same time.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9411 | 制造商:AD 制造商全稱:Analog Devices 功能描述:10-Bit, 170/200 MSPS 3.3 V A/D Converter |
| AD9411/PCB | 制造商:Analog Devices 功能描述: |
| AD9411BSV-170 | 制造商:Analog Devices 功能描述:ADC Single Pipelined 170Msps 10-bit Parallel/LVDS 100-Pin TQFP EP 制造商:Analog Devices 功能描述:IC 10BIT ADC SMD 9411 TQFP100 |
| AD9411BSV-200 | 制造商:Analog Devices 功能描述:ADC Single Pipelined 200Msps 10-bit Parallel/LVDS 100-Pin TQFP EP |
| AD9411BSVZ-170 | 功能描述:IC ADC 10BIT 170MSPS 100TQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 位數(shù):12 采樣率（每秒）:3M 數(shù)據(jù)接口:- 轉(zhuǎn)換器數(shù)目:- 功率耗散（最大）:- 電壓電源:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:SOT-23-6 供應(yīng)商設(shè)備封裝:SOT-23-6 包裝:帶卷 (TR) 輸入數(shù)目和類型:- |
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