參數(shù)資料
型號(hào)： AD9273BSVZ-40
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 36/48頁(yè)
文件大?。?/td> 0K
描述： IC ADC OCT 12BIT 40MSPS 100-TQFP
標(biāo)準(zhǔn)包裝： 1
類(lèi)型： AAF，ADC，交叉點(diǎn)開(kāi)關(guān)，LNA，VGA
分辨率（位）： 12 b
采樣率（每秒）： 40M
數(shù)據(jù)接口： 串行，SPI?
電壓電源： 模擬和數(shù)字
電源電壓： 1.8V，3V
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 100-TQFP 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝： 100-TQFP-EP（14x14）
包裝： 托盤(pán)
AD9273
Rev. B | Page 41 of 48
Table 17. AD9273 Memory Map Register
Addr.
(Hex)
Register Name
Bit 7
(MSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSB)
Default
Value
Default Notes/
Comments
Chip Configuration Registers
00
CHIP_PORT_CONFIG
0
LSB first
1 = on
0 = off
(default)
Soft
reset
1 = on
0 = off
(default)
1
Soft
reset
1 = on
0 = off
(default)
LSB first
1 = on
0 = off
(default)
0
0x18
The nibbles
should be
mirrored so that
LSB- or MSB-first
mode is set cor-
rectly regardless
of shift mode.
01
CHIP_ID
Chip ID Bits[7:0]
(AD9273 = 0x2F, default)
Read
only
Default is unique
chip ID, different
for each device.
This is a read-only
register.
02
CHIP_GRADE
X
Child ID[5:4]
(identify device
variants of Chip ID)
00 = 40 MSPS
(default)
01 = 25 MSPS
10 = 50 MSPS
X
0x00
Child ID used to
differentiate
graded devices.
Device Index and Transfer Registers
04
DEVICE_INDEX_2
X
Data
Channel
H
1 = on
(default)
0 = off
Data
Channel
G
1 = on
(default)
0 = off
Data
Channel
F
1 = on
(default)
0 = off
Data
Channel
E
1 = on
(default)
0 = off
0x0F
Bits are set to
determine which
on-chip device
receives the next
write command.
05
DEVICE_INDEX_1
X
Clock
Channel
DCO±
1 = on
0 = off
(default)
Clock
Channel
FCO±
1 = on
0 = off
(default)
Data
Channel
D
1 = on
(default)
0 = off
Data
Channel
C
1 = on
(default)
0 = off
Data
Channel
B
1 = on
(default)
0 = off
Data
Channel
A
1 = on
(default)
0 = off
0x0F
Bits are set to
determine which
on-chip device
receives the next
write command.
FF
DEVICE_UPDATE
X
SW
transfer
1 = on
0 = off
(default)
0x00
Synchronously
transfers data
from the master
shift register to
the slave.
ADC Functions Registers
08
Modes
X
0
Internal power-down mode
000 = chip run (default)
001 = full power-down
010 = standby
011 = reset
100 = CW mode (TGC PDWN)
0x00
Determines
various generic
modes of chip
operation
(global).
09
Clock
X
Duty
cycle
stabilizer
1 = on
(default)
0 = off
0x01
Turns the internal
duty cycle stabilizer
on and off
(global).
0D
TEST_IO
User test mode
00 = off (default)
01 = on, single
alternate
10 = on, single once
11 = on, alternate once
Reset PN
long
gen
1 = on
0 = off
(default)
Reset PN
short
gen
1 = on
0 = off
(default)
Output test mode—see Table 12
0000 = off (default)
0001 = midscale short
0010 = +FS short
0011 = FS short
0100 = checkerboard output
0101 = PN sequence long
0110 = PN sequence short
0111 = one-/zero-word toggle
1000 = user input
1001 = 1-/0-bit toggle
1010 = 1× sync
1011 = one bit high
1100 = mixed bit frequency (format
determined by the OUTPUT_MODE register)
0x00
When this register
is set, the test data
is placed on the
output pins in
place of normal
data. (Local, expect
for PN sequence.)
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