參數(shù)資料
型號: AD9271BSVZRL-40
廠商: Analog Devices Inc
文件頁數(shù): 36/60頁
文件大?。?/td> 0K
描述: IC ADC OCT 12BIT 40MSPS 100-TQFP
標(biāo)準(zhǔn)包裝: 1,000
位數(shù): 12
采樣率(每秒): 40M
數(shù)據(jù)接口: 串行,SPI?
轉(zhuǎn)換器數(shù)目: 8
功率耗散(最大): 1.28W
電壓電源: 單電源
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 100-TQFP 裸露焊盤
供應(yīng)商設(shè)備封裝: 100-TQFP-EP(14x14)
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 8 個單端,單極;8 個差分,單極
AD9271
Rev. B | Page 41 of
60
APPLICATIONS INFORMATION
DESIGN GUIDELINES
Before starting design and layout of the AD9271 as a system, it
is recommended that the designer become familiar with these
guidelines, which discuss the special circuit connections and
layout requirements needed for certain pins.
Power and Ground Recommendations
When connecting power to the AD9271, it is recommended
that two separate 1.8 V supplies be used: one for analog (AVDD)
and one for digital (DRVDD). The AD9271 also requires a
3.3 V supply (CWVDD) for the crosspoint section. If only one
1.8 V supply is available, it should be routed to the AVDD first
and then tapped off and isolated with a ferrite bead or a filter
choke preceded by decoupling capacitors for the DRVDD. The
user should employ several decoupling capacitors on all supplies
to cover both high and low frequencies. These capacitors should
be located close to the point of entry at the PC board level and
close to the parts with minimal trace lengths.
A single PC board ground plane should be sufficient when
using the AD9271. With proper decoupling and smart parti-
tioning of the PC board’s analog, digital, and clock sections,
optimum performance can be easily achieved.
Exposed Paddle Thermal Heat Slug Recommendations
It is required that the exposed paddle on the underside of the
device be connected to the analog ground (AGND) to achieve
the best electrical and thermal performance of the AD9271. An
exposed continuous copper plane on the PCB should mate to
the AD9271 exposed paddle, Pin 0. The copper plane should
have several vias to achieve the lowest possible resistive thermal
path for heat dissipation to flow through the bottom of the PCB.
These vias should be filled or plugged with nonconductive epoxy.
To maximize the coverage and adhesion between the device and
PCB, partition the continuous copper pad by overlaying a silk-
screen or solder mask to divide it into several uniform sections.
This ensures several tie points between the two during the reflow
process. Using one continuous plane with no partitions guarantees
only one tie point between the AD9271 and PCB. See Figure 72
for a PCB layout example. For more detailed information on
packaging and for more PCB layout examples, see the AN-772
Application Note.
SILKSCREEN PARTITION
PIN 1 INDICATOR
06
30
4-
06
9
Figure 72. Typical PCB Layout
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