參數(shù)資料
型號: AD9271BSVZRL-40
廠商: Analog Devices Inc
文件頁數(shù): 28/60頁
文件大小: 0K
描述: IC ADC OCT 12BIT 40MSPS 100-TQFP
標準包裝: 1,000
位數(shù): 12
采樣率(每秒): 40M
數(shù)據(jù)接口: 串行,SPI?
轉(zhuǎn)換器數(shù)目: 8
功率耗散(最大): 1.28W
電壓電源: 單電源
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 100-TQFP 裸露焊盤
供應商設備封裝: 100-TQFP-EP(14x14)
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 8 個單端,單極;8 個差分,單極
AD9271
Rev. B | Page 34 of
60
External Reference Operation
Internal Reference Operation
The use of an external reference may be necessary to enhance
the gain accuracy of the ADC or to improve thermal drift charac-
teristics. Figure 69 shows the typical drift characteristics of the
internal reference in 1 V mode.
A comparator within the AD9271 detects the potential at the
SENSE pin and configures the reference. If SENSE is grounded,
the reference amplifier switch is connected to the internal
resistor divider (see Figure 66), setting VREF to 1 V.
When the SENSE pin is tied to AVDD, the internal reference is
disabled, allowing the use of an external reference. The external
reference is loaded with an equivalent 6 kΩ load. An internal
reference buffer generates the positive and negative full-scale
references, REFT and REFB, for the ADC core. Therefore, the
external reference must be limited to a nominal voltage of 1.0 V.
The REFT and REFB pins establish their input span of the ADC
core from the reference configuration. The analog input full-
scale range of the ADC equals twice the voltage at the reference
pin for either an internal or an external reference configuration.
1F
0.1F
VREF
SENSE
0.5V
REFT
0.1F
4.7F
0.1F
REFB
SELECT
LOGIC
ADC
CORE
+
VIN–
VIN+
4
06
30
4-
0
6
6304-
065
.5
5
0
–5
–10
–15
–20
–25
03
3.0
2.5
2.0
1.5
1.0
0.5
06
30
4-
0
17
V
RE
F
E
RRO
R
(
%
)
CURRENT LOAD (mA)
Figure 66. Internal Reference Configuration
Figure 68. VREF Accuracy vs. Load, AD9271-50
0.02
0
–0.02
–0.04
–0.06
–0.08
–0.10
–0.12
–0.14
–0.16
–0.18
–0.20
–40
80
60
40
20
0
–20
06
30
4-
01
5
V
R
E
F
E
RRO
R
(%
)
TEMPERATURE (°C)
VIN–
VIN+
1F*
0.1F*
VREF
SENSE
AVDD
0.5V
REFT
0.1F
4.7F
0.1F
REFB
SELECT
LOGIC
ADC
CORE
+
EXTERNAL
REFERENCE
*OPTIONAL.
Figure 69. Typical VREF Drift, AD9271-50
0
Figure 67. External Reference Operation
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