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參數(shù)資料
| 型號： | AD9262BCPZRL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 19/32頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 16BIT 2.5MHZ 64LFCSP |
| 設(shè)計資源： | Interfacing ADL5382 to AD9262 as an RF-to-Bits Solution (CN0062) |
| 標(biāo)準包裝： | 750 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 160M |
| 數(shù)據(jù)接口： | 串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 功率耗散（最大）： | 640mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 64-LFCSP-VQ（9x9） |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 2 個單端，雙極；1 個差分，單極 |
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AD9262
Rev. A | Page 26 of 32
SERIAL PORT INTERFACE (SPI)
The AD9262 serial port interface (SPI) allows the user to configure
the converter for specific functions or operations through a
structured register space provided inside the ADC. This provides
the user added flexibility and customization depending on the
application. Addresses are accessed via the serial port and can
be written to or read from via the port. Memory is organized
into bytes that are further divided into fields, as documented in
the Memory Map section. For detailed operational information,
see the AN-877 Application Note, Interfacing to High Speed
ADCs via SPI.
CONFIGURATION USING THE SPI
As summarized in Table 22, three pins define the SPI of this ADC.
The SCLK pin synchronizes the read and write data presented
to the ADC. The SDIO pin allows data to be sent and read from
the internal ADC memory map registers. The CSB pin is an active
low control that enables or disables the read and write cycles.
Table 22. Serial Port Interface Pins
Pin Name
Description
SCLK
SCLK (serial clock) is the serial shift clock. SCLK
synchronizes serial interface reads and writes.
SDIO
SDIO (serial data input/output) is an input and
output depending on the instruction being sent
and the relative position in the timing frame.
CSB
CSB (chip select bar) is an active low control that
gates the read and write cycles.
The falling edge of CSB in conjunction with the rising edge of
SCLK determines the start of the framing. Figure 60 and Table 23
provide an example of the serial timing and its definitions.
Other modes involving CSB are available. CSB can be held low
indefinitely to permanently enable the device (this is called
streaming). CSB can stall high between bytes to allow for addi-
tional external timing. When CSB is tied high, SPI functions are
placed in a high impedance mode.
During an instruction phase, a 16-bit instruction is transmitted.
Data follows the instruction phase, and the length is determined
by the W0 bit and the W1 bit. All data is composed of 8-bit words.
The first bit of each individual byte of serial data indicates whether
a read or write command is issued. This allows the serial data
input/output (SDIO) pin to change direction from an input to
an output.
In addition to word length, the instruction phase determines if
the serial frame is a read or write operation, allowing the serial
port to be used to both program the chip and to read the contents
of the on-chip memory. If the instruction is a readback opera-
tion, performing a readback causes the serial data input/output
(SDIO) pin to change direction from an input to an output at the
appropriate point in the serial frame.
Data can be sent in MSB-first or in LSB-first mode. MSB first is
the default setting on power-up and can be changed via the
configuration register. For more information, see the AN-877
Application Note, Interfacing to High Speed ADCs via SPI.
Table 23. SPI Timing Diagram Specifications
Parameter
Description
tSDS
Setup time between data and rising edge of SCLK
tSDH
Hold time between data and rising edge of SCLK
tSCLK
Period of the clock
tSS
Setup time between CSB and SCLK
tSH
Hold time between CSB and SCLK
tSHIGH
Minimum period that SCLK should be in a logic
high state
tSLOW
Minimum period that SCLK should be in a logic
low state
DON’T CARE
SDIO
SCLK
CSB
tSS
tSDH
tSHIGH
tSCLK
tSLOW
tSDS
tSH
R/W
W1
W0
A12
A11
A10
A9
A8
A7
D5
D4
D3
D2
D1
D0
0
777
2-
05
4
Figure 60. Serial Port Interface Timing Diagram
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| AD9262BCPZRL7-10 | 功能描述:IC ADC 16BIT 10MHZ 64LFCSP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應(yīng)商設(shè)備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類型:1 個單端，雙極 |
| AD9262BCPZRL7-5 | 功能描述:IC ADC 16BIT 5MHZ 64LFCSP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應(yīng)商設(shè)備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類型:1 個單端，雙極 |
| AD9262-EBZ | 制造商:Analog Devices 功能描述:Evaluation Board For AD9262BCPZ 制造商:Analog Devices 功能描述:16 BIT DUAL BANDWIDTH ADC EB - Boxed Product (Development Kits) 制造商:Analog Devices 功能描述:A/D Converter Eval. Board 制造商:Analog Devices 功能描述:A/D Converter Eval. Board; Silicon Manufacturer:Analog Devices; Silicon Core Number:AD9262; Kit Application Type:Data Converter; Application Sub Type:ADC; Kit Contents:Software, Evaluation Board |
| AD9265 | 制造商:AD 制造商全稱:Analog Devices 功能描述:16-Bit, 125 MSPS/105 MSPS/80 MSPS 1.8 V Analog-to-Digital Converter |
| AD9265-105EBZ | 功能描述:數(shù)據(jù)轉(zhuǎn)換 IC 開發(fā)工具 16 Bit 105 Msps high SNR 1.8 RoHS:否 制造商:Texas Instruments 產(chǎn)品:Demonstration Kits 類型:ADC 工具用于評估:ADS130E08 接口類型:SPI 工作電源電壓:- 6 V to + 6 V |
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