參數(shù)資料
型號(hào): AD9257-65EBZ
廠商: Analog Devices Inc
文件頁(yè)數(shù): 36/40頁(yè)
文件大?。?/td> 0K
描述: BOARD EVAL FOR AD9257
標(biāo)準(zhǔn)包裝: 1
ADC 的數(shù)量: 8
位數(shù): 14
采樣率(每秒): 65M
數(shù)據(jù)接口: 串行,SPI?
輸入范圍: 2 Vpp
在以下條件下的電源(標(biāo)準(zhǔn)): 55mW @ 65MSPS
工作溫度: -40°C ~ 85°C
已用 IC / 零件: AD9257
已供物品:
Data Sheet
AD9257
Rev. A | Page 5 of 40
Parameter1
Temp
AD9257-40
AD9257-65
Unit
Min
Typ
Max
Min
Typ
Max
CROSSTALK2
25°C
100
98
dB
Crosstalk (Overrange Condition)3
25°C
92
94
dB
POWER SUPPLY REJECTION RATIO (PSRR)4
25°C
AVDD
52
dB
DRVDD
73
71
dB
ANALOG INPUT BANDWIDTH, FULL POWER
25°C
650
MHz
1
See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed.
2
Crosstalk is measured at 10 MHz with 1.0 dBFS analog input on one channel and no input on the adjacent channel.
3
Overrange condition is 3 dB above the full-scale input range.
4
PSRR is measured by injecting a sinusoidal signal at 10 MHz to the power supply pin and measuring the output spur on the FFT. PSRR is calculated as the ratio of the
amplitudes of the spur voltage over the pin voltage, expressed in decibels.
DIGITAL SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = 1.0 dBFS, unless otherwise noted.
Table 3.
Parameter1
Temp
Min
Typ
Max
Unit
CLOCK INPUTS (CLK+, CLK)
Logic Compliance
CMOS/LVDS/LVPECL
Differential Input Voltage2
Full
0.2
3.6
V p-p
Input Voltage Range
Full
AGND 0.2
AVDD + 0.2
V
Input Common-Mode Voltage
Full
0.9
V
Input Resistance (Differential)
25°C
15
k
Input Capacitance
25°C
4
pF
LOGIC INPUTS (PDWN, SYNC, SCLK)
Logic 1 Voltage
Full
1.2
AVDD + 0.2
V
Logic 0 Voltage
Full
0
0.8
V
Input Resistance
25°C
30
k
Input Capacitance
25°C
2
pF
LOGIC INPUT (CSB)
Logic 1 Voltage
Full
1.2
AVDD + 0.2
V
Logic 0 Voltage
Full
0
0.8
V
Input Resistance
25°C
26
k
Input Capacitance
25°C
2
pF
LOGIC INPUT (SDIO)
Logic 1 Voltage
Full
1.2
AVDD + 0.2
V
Logic 0 Voltage
Full
0
0.8
V
Input Resistance
25°C
26
k
Input Capacitance
25°C
5
pF
LOGIC OUTPUT (SDIO)3
Logic 1 Voltage (IOH = 800 μA)
Full
1.79
V
Logic 0 Voltage (IOL = 50 μA)
Full
0.05
V
DIGITAL OUTPUTS (D± x), ANSI-644
Logic Compliance
LVDS
Differential Output Voltage (VOD)
Full
247
350
454
mV
Output Offset Voltage (VOS)
Full
1.13
1.21
1.38
V
Output Coding (Default)
Twos complement
DIGITAL OUTPUTS (D± x), LOW POWER, REDUCED SIGNAL OPTION
Logic Compliance
LVDS
Differential Output Voltage (VOD)
Full
150
200
250
mV
Output Offset Voltage (VOS)
Full
1.13
1.21
1.38
V
Output Coding (Default)
Twos complement
1
See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed.
2
This is specified for LVDS and LVPECL only.
3
This is specified for 13 SDIO/DFS pins sharing the same connection.
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