參數(shù)資料
型號(hào): AD9246BCPZRL7-125
廠商: Analog Devices Inc
文件頁(yè)數(shù): 19/44頁(yè)
文件大?。?/td> 0K
描述: IC ADC 14BIT 125MSPS 48-LFCSP
設(shè)計(jì)資源: Using AD8376 to Drive Wide Bandwidth ADCs for High IF AC-Coupled Appls (CN0002)
Driving AD9233/46/54 ADCs in AC-Coupled Baseband Appls (CN0051)
標(biāo)準(zhǔn)包裝: 750
位數(shù): 14
采樣率(每秒): 125M
數(shù)據(jù)接口: 串行,SPI?
轉(zhuǎn)換器數(shù)目: 3
功率耗散(最大): 425mW
電壓電源: 單電源
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 48-VFQFN 裸露焊盤,CSP
供應(yīng)商設(shè)備封裝: 48-LFCSP-VQ(7x7)
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 2 個(gè)單端,單極;1 個(gè)差分,單極
AD9246
Rev. A | Page 26 of 44
Addr.
(Hex)
Parameter Name
Bit 7
(MSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSB)
Default
Value
(Hex)
Default Notes/
Comments
Flexible ADC Functions
10
offset
Digital Offset Adjust<5:0>
011111
011110
011101
000010
000001
000000
111111
111110
111101
...
100001
100000
Offset in LSBs
+31
+30
+29
+2
+1
0 (Default)
1
2
3
31
32
0x00
Adjustable for
offset inherent
in the converter.
See the
section.
0D
test_io
PN23
0 =
normal
(Default)
1 = reset
PN9
0 =
normal
(Default)
1 =
reset
Global Output Test Options
000—off (Default)
001—midscale short
010—+FS short
011—FS short
100—checker board output
101—PN 23 sequence
110—PN 9
111—one/zero word toggle
0x00
See the
14
output_mode
Output Driver
Configuration
00 for DRVDD = 2.5 V to
3.3 V (Default)
10 for DRVDD = 1.8 V
Open
Output
Disable
1—
disabled
0—
enabled1
Open
Output
Data
Invert
1 =
invert
Data Format Select
00—offset binary
(default)
01—twos
complement
10—Gray Code
0x00
Configures the
outputs and
the format of
the data.
16
output_phase
Output Clock
Polarity
1 = inverted
0 = normal
(Default)
Open
0x00
See the
section.
18
VREF
Internal Reference
Resistor Divider
00—VREF = 1.25 V
01—VREF = 1.5 V
10—VREF = 1.75 V
11—VREF = 2.00 V
(Default)
Open
0xC0
See the
section.
1 External output enable (OEB) pin must be high.
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