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參數(shù)資料
| 型號(hào)： | AD9243EB |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Complete 14-Bit, 3.0 MSPS Monolithic A/D Converter |
| 中文描述： | 完整的14位，3.0 MSPS的單片機(jī)的A / D轉(zhuǎn)換器 |
| 文件頁數(shù)： | 10/24頁 |
| 文件大?。?/td> | 545K |
| 代理商： | AD9243EB |
AD9243
REV. A
–10–
10
m
F
VINA
VINB
SENSE
AD9243
0.1
m
F
R
S
*
V
CC
V
EE
R
S
*
VREF
REFCOM
*OPTIONAL SERIES RESISTOR
Figure 25. Series Resistor Isolates Switched-Capacitor
SHA Input from Op Amp. Matching Resistors Improve
SNR Performance
The optimum size of this resistor is dependent on several factors
which include the AD9243 sampling rate, the selected op amp,
and the particular application.
In most applications, a 30
to
50
resistor is sufficient.
However, some applications may re-
quire a larger resistor value to reduce the noise bandwidth or
possibly limit the fault current in an overvoltage condition.
Other applications may require a larger resistor value as part of
an anti-aliasing filter. In any case, since the THD performance
is dependent on the series resistance and the above mentioned
factors, optimizing this resistor value for a given application is
encouraged.
A slight improvement in SNR performance and dc offset perfor-
mance is achieved by matching the input resistance connected
to VINA and VINB. The degree of improvement is dependent on
the resistor value and the sampling rate. For series resistor
values greater than 100
, the use of a matching resistor is
encouraged.
The noise or small-signal bandwidth of the AD9243 is the same
as its full-power bandwidth. For noise sensitive applications, the
excessive bandwidth may be detrimental and the addition of a
series resistor and/or shunt capacitor can help limit the wide-
band noise at the A/D’s input by forming a low-pass filter.
Note, however, that the combination of this series resistance
with the equivalent input capacitance of the AD9243 should be
evaluated for those time-domain applications that are sensitive
to the input signal’s absolute settling time. In applications where
harmonic distortion is not a primary concern, the series resis-
tance may be selected in combination with the SHA’s nominal
16 pF of input capacitance to set the filter’s 3 dB cutoff frequency.
A better method of reducing the noise bandwidth, while possi-
bly establishing a real pole for an antialiasing filter, is to add
some additional shunt capacitance between the input (i.e.,
VINA and/or VINB) and analog ground. Since this additional
shunt capacitance combines with the equivalent input capaci-
tance of the AD9243, a lower series resistance can be selected to
establish the filter’s cutoff frequency while not degrading the
distortion performance of the device. The shunt capacitance
also acts like a charge reservoir, sinking or sourcing the addi-
tional charge required by the hold capacitor, C
H
, further reduc-
ing current transients seen at the op amp’s output.
The effect of this increased capacitive load on the op amp driv-
ing the AD9243 should be evaluated. To optimize performance
when noise is the primary consideration, increase the shunt
capacitance as much as the transient response of the input signal
will allow. Increasing the capacitance too much may adversely
affect the op amp’s settling time, frequency response, and dis-
tortion performance.
Table I. Analog Input Configuration Summary
Input
Connection
Single-Ended
Input
Span (V)
2
Input Range (V)
VINA
1
0 to 2
Figure
#
32, 33
Coupling
DC
VINB
1
1
Comments
Best for stepped input response applications, suboptimum
THD and noise performance, requires
±
5 V op amp.
2
×
VREF
0 to
2
×
VREF
VREF
32, 33
Same as above but with improved noise performance due to
increase in dynamic range. Headroom/settling time require-
ments of
±
5 op amp should be evaluated.
5
0 to 5
2.5
32, 33
Optimum noise performance, excellent THD performance. Requires
op amp with VCC > +5 V due to insufficient headroom @ 5 V.
2
×
VREF
2.5 – VREF
to
2.5 + VREF
2.5
39
Optimum THD performance with VREF = 1, noise performance
improves while THD performance degrades as VREF increases
to 2.5 V. Single supply operation (i.e., +5 V) for many op amps.
Single-Ended
AC
2 or
2
×
VREF
0 to 1 or
0 to 2
×
VREF
1 or VREF
34
Suboptimum ac performance due to input common-mode
level not biased at optimum midsupply level (i.e., 2.5 V).
5
2
×
VREF
0 to 5
2.5
34
Optimum noise performance, excellent THD performance.
2.5 – VREF
to
2.5 + VREF
2.5
35
Flexible input range, Optimum THD performance with
VREF = 1. Noise performance improves while THD perfor-
mance degrades as VREF increases to 2.5 V.
Differential
AC or
DC
2
2 to 3
3 to 2
29–31
Optimum full-scale THD and SFDR performance well be-
yond the A/Ds Nyquist frequency.
2
×
VREF
2.5 – VREF/2
to
2.5 + VREF/2
2.5 + VREF/2
to
2.5 – VREF/2
29–31
Same as 2 V to 3 V input range with the exception that full-scale
THD and SFDR performance can be traded off for better noise
performance.
5
1.75 to 3.25
3.25 to 1.75
29–31
Widest dynamic range (i.e., ENOBs) due to Optimum Noise
performance.
NOTE
1
VINA and VINB can be interchanged if signal inversion is required.
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PDF描述 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9243-EB | 制造商:Analog Devices 功能描述:Evaluation Board For AD9243 制造商:Analog Devices 功能描述:DEV TOOLS, EVAL BD FOR AD9243 - Bulk |
| AD9244 | 制造商:AD 制造商全稱:Analog Devices 功能描述:14-Bit, 40/65 MSPS Monolithic A/D Converter |
| AD9244_05 | 制造商:AD 制造商全稱:Analog Devices 功能描述:14-Bit, 40 MSPS/65 MSPS A/D Converter |
| AD9244-40PCB | 制造商:Analog Devices 功能描述:EVAL BD FOR AD9244 ,14BIT, 40/65MSPS A/D CNVRTR - Bulk |
| AD9244-40PCBZ | 制造商:Analog Devices 功能描述:Evaluation Board For Ad9244-40 制造商:Analog Devices 功能描述:14 BIT 40/65 MSPS IF SAMPLING ADC - Bulk |
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