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參數(shù)資料
| 型號： | AD9238BST-65 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 12-Bit, 20/40/65 MSPS Dual A/D Converter |
| 中文描述： | 2-CH 12-BIT FLASH METHOD ADC, PARALLEL ACCESS, PQFP64 |
| 封裝： | LEAD FREE, MS-026-BBD, LQFP-64 |
| 文件頁數(shù)： | 15/24頁 |
| 文件大?。?/td> | 1737K |
| 代理商： | AD9238BST-65 |
AD9238
–15–
The internal duty cycle stabilizer can be enabled on the AD9238-65
using the DCS pin. This provides a stable 50% duty cycle to
internal circuits.
The length of the output data lines and loads placed on them should
be minimized to reduce transients within the AD9238. These
transients can detract from the converter’s dynamic performance.
The lowest typical conversion rate of the AD9238 is 1 MSPS. At
clock rates below 1 MSPS, dynamic performance may degrade.
DATA FORMAT
The AD9238 data output format can be configured for either
twos complement or offset binary. This is controlled by the Data
Format Select pin (DFS). Connecting DFS to AGND will pro-
duce offset binary output data. Conversely, connecting DFS to
AVDD will format the output data as twos complement.
The output data from the dual A/D converters can be multiplexed
onto a single 12-bit output bus. The multiplexing is accomplished
by toggling the MUX_SELECT bit, which directs channel data
to the same or opposite channel data port. When MUX_SELECT
is logic high, the Channel A data is directed to Channel A output
bus, and Channel B data is directed to the Channel B output bus.
When MUX_SELECT is logic low, the channel data is reversed, i.e.,
Channel A data is directed to the Channel B output bus and
Channel B data is directed to the Channel A output bus. By
toggling the MUX_SELECT bit, multiplexed data is available
on either of the output data ports.
If the ADCs are run with synchronized timing, this same clock can
be applied to the MUX_SELECT bit. After the MUX_SELECT
rising edge, either data port will have the data for its respective
channel; after the falling edge, the alternate channel’s data will be
placed on the bus. Typically, the other unused bus would be
disabled by setting the appropriate OEB high to reduce power
consumption and noise. Figure 7 shows an example of multiplex
mode. When multiplexing data, the data rate is two times the
sample rate. Note that both channels must remain active in this
mode and that each channel's power-down pin must remain low.
VOLTAGE REFERENCE
A stable and accurate 0.5 V voltage reference is built into the
AD9238. The input range can be adjusted by varying the reference
voltage applied to the AD9238, using either the internal reference
with different external resistor configurations or an externally
applied reference voltage. The input span of the ADC tracks refer-
ence voltage changes linearly.
If the ADC is being driven differentially through a transformer,
the reference voltage can be used to bias the center tap (common-
mode voltage).
The Shared Reference mode allows the user to connect the refer-
ences from the dual ADCs together externally for superior gain
and offset matching performance. If the ADCs are to function
independently, the reference decoupling can be treated inde-
pendently and can provide superior isolation between the dual
channels. To enable Shared Reference mode, the SHARED_REF
pin must be tied high and external differential references must
be externally shorted. (REFT_A must be externally shorted to
REFT_B and REFB_A must be shorted to REFB_B.)
Internal Reference Connection
A comparator within the AD9238 detects the potential at the
SENSE pin and configures the reference into four possible states,
which are summarized in Table I. If SENSE is grounded, the refer-
ence amplifier switch is connected to the internal resistor divider
(see Figure 8), setting V
REF
to 1 V. Connecting the SENSE pin to
V
REF
switches the reference amplifier output to the SENSE pin,
completing the loop and providing a 0.5 V reference output. If a
resistor divider is connected as shown in Figure 9, the switch will
again be set to the SENSE pin. This will put the reference ampli-
fier in a noninverting mode with the V
REF
output defined as follows:
V
.
(
×
0 5
In all reference configurations, REFT and REFB drive the ADC
core and establish its input span. The input range of the ADC
always equals twice the voltage at the reference pin for either an
internal or an external reference.
R
R )
1
REF
=
+
1
2
VIN+
VIN–
10
F
10
F
0.1
F
0.1
F
REFT
ADC
CORE
SELECT
LOGIC
SENSE
0.1
F
0.5V
AD9238
REFB
0.1
F
V
REF
Figure 8. Internal Reference Configuration
Table I. Reference Configuration Summary
Resulting Differential
Span (V p-p)
2
External Reference
1.0
2
V
REF
(See Figure 9)
2.0
Selected Mode
External Reference
Internal Fixed Reference
Programmable Reference
Internal Fixed Reference
SENSE Voltage
AVDD
V
REF
0.2 V to V
REF
AGND to 0.2 V
Resulting V
REF
(V)
N/A
0.5
0.5
(1 + R2/R1)
1.0
REV. A
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9238BST-65PCB | 制造商:Analog Devices 功能描述:Evaluation Board For AD9238 Dual A/D Converter ,12-Bit, 20 MSPS/40 MSPS/65 MSPS 制造商:Rochester Electronics LLC 功能描述:DUAL 12 BIT 3V CMOS 20/40/65 MSPS ADC - Bulk |
| AD9238BST-65PCBZ | 制造商:Analog Devices 功能描述:DUAL 12 BIT 3V CMOS 20/40/65 MSPS ADC - Bulk |
| AD9238BSTRL-20 | 制造商:Rochester Electronics LLC 功能描述:DUAL 12 BIT 3V CMOS 20/40/65 MSPS ADC - Bulk 制造商:Analog Devices 功能描述: |
| AD9238BSTRL-40 | 功能描述:IC ADC 12BIT DUAL 40MSPS 64-LQFP RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 位數(shù):12 采樣率（每秒）:3M 數(shù)據(jù)接口:- 轉(zhuǎn)換器數(shù)目:- 功率耗散（最大）:- 電壓電源:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:SOT-23-6 供應(yīng)商設(shè)備封裝:SOT-23-6 包裝:帶卷 (TR) 輸入數(shù)目和類型:- |
| AD9238BSTRL-65 | 功能描述:IC ADC 12BIT DUAL 65MSPS 64-LQFP RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 位數(shù):12 采樣率（每秒）:3M 數(shù)據(jù)接口:- 轉(zhuǎn)換器數(shù)目:- 功率耗散（最大）:- 電壓電源:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:SOT-23-6 供應(yīng)商設(shè)備封裝:SOT-23-6 包裝:帶卷 (TR) 輸入數(shù)目和類型:- |
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