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參數(shù)資料
| 型號： | AD9238BST-65 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 12-Bit, 20/40/65 MSPS Dual A/D Converter |
| 中文描述： | 2-CH 12-BIT FLASH METHOD ADC, PARALLEL ACCESS, PQFP64 |
| 封裝： | LEAD FREE, MS-026-BBD, LQFP-64 |
| 文件頁數(shù)： | 1/24頁 |
| 文件大?。?/td> | 1737K |
| 代理商： | AD9238BST-65 |
Information furnished by Analog Devices is be ieved to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
that may result from its use. No license is granted by implication or oth-
erwise under any patent or patent rights of Analog Devices. Trademarks
and registered trademarks are the property of their respective owners.
Tel: 781/329-4700 www.analog.com
AD923812-Bit, 20/40/65 MSPS
Dual A/D Converter
FUNCTIONAL BLOCK DIAGRAM
SHA
A/D
SHA
A/D
CLOCK
DUTY CYCLE
STABILIZER
MODE
SELECT
OEB_A
OTR_A
D11_A
D0_A
MUX_SELECT
CLK_A
CLK_B
DCS
DFS
PDWN_A
PDWN_B
SHARED_REF
OEB_B
OTR_B
D11_B
D0_B
DRGND
AGND
DRVDD
AVDD
0.5V
VIN+_A
VIN–_A
REFT_A
REFB_A
VREF
SENSE
AGND
REFB_B
REFT_B
VIN–_B
VIN+_B
O
B
O
B
FEATURES
Integrated Dual 12-Bit Analog-to-Digital Converters
Single 3 V Supply Operation (2.7 V to 3.6 V)
SNR = 70 dBc (to Nyquist, AD9238-65)
SFDR = 85 dBc (to Nyquist, AD9238-65)
Low Power: 600 mW at 65 MSPS
Differential Input with 500 MHz 3 dB Bandwidth
On-Chip Reference and SHA
Flexible Analog Input: 1 V p-p to 2 V p-p Range
Offset Binary or Twos Complement Data Format
Clock Duty Cycle Stabilizer
APPLICATIONS
Ultrasound Equipment
IF Sampling in Communications Receivers:
IS-95, CDMA One, IMT-2000
Battery-Powered Instruments
Hand-Held Scopemeters
Low Cost Digital Oscilloscopes
PRODUCT HIGHLIGHTS
1. Integrated, dual version of the AD9235—a 12-bit,
20 MSPS/40 MSPS/65 MSPS ADC.
2. Speed grade options of 20 MSPS, 40 MSPS, and 65 MSPS
allow flexibility between power, cost, and performance to suit
an application.
3. The AD9238 operates from a single 3 V power supply and
features a separate digital output driver supply to accommo-
date 2.5 V and 3.3 V logic families.
4. Low power consumption:
AD9238-20 operating at 20 MSPS consumes a low 180 mW.
AD9238-40 operating at 40 MSPS consumes a low 330 mW.
AD9238-65 operating at 65 MSPS consumes a low 600 mW.
5. The patented SHA input maintains excellent performance for
input frequencies up to 100 MHz and can be configured for
single-ended or differential operation.
6. Typical channel isolation of 80 dB @ f
IN
= 10 MHz.
7. The clock duty cycle stabilizer (AD9238-65 only) maintains
performance over a wide range of clock duty cycles.
8. The OTR output bits indicate when either input signal is
beyond the selected input range.
9. Multiplexed data output option enables single-port operation
from either data port A or data port B.
GENERAL DESCRIPTION
The AD9238 is a dual, 3 V, 12-bit, 20 MSPS/40 MSPS/65 MSPS
analog-to-digital converter. It features dual high performance
sample-and-hold amplifiers and an integrated voltage reference.
The AD9238 uses a multistage differential pipelined architecture
with output error correction logic to provide 12-bit accuracy and
guarantee no missing codes over the full operating temperature
range at data rates up to 65 MSPS.
The wide bandwidth, differential SHA allows for a variety of
user selectable input ranges and offsets including single-ended
applications. It is suitable for various applications including multi-
plexed systems that switch full-scale voltage levels in successive
channels and for sampling inputs at frequencies well beyond the
Nyquist rate. The AD9238 is suitable for applications in commu-
nications, imaging, and medical ultrasound.
Dual single-ended clock inputs are used to control all internal con-
version cycles. A duty cycle stabilizer is available on the AD9238-65
and can compensate for wide variations in the clock duty cycle,
allowing the converters to maintain excellent performance. The
digital output data is presented in either straight binary or twos
complement format. Out-of-range signals indicate an overflow
condition, which can be used with the most significant bit to deter-
mine low or high overflow.
Fabricated on an advanced CMOS process, the AD9238 is avail-
able in a space saving 64-lead LQFP and is specified over the
industrial temperature range (–40°C to +85°C).
REV. A
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD9238BSTRL-20 | 12-Bit, 20/40/65 MSPS Dual A/D Converter |
| AD9238BSTRL-40 | 12-Bit, 20/40/65 MSPS Dual A/D Converter |
| AD9238BSTRL-65 | 12-Bit, 20/40/65 MSPS Dual A/D Converter |
| AD9240 | Complete 14-Bit, 10 MSPS Monolithic A/D Converter |
| AD9240AS | Complete 14-Bit, 10 MSPS Monolithic A/D Converter |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9238BST-65PCB | 制造商:Analog Devices 功能描述:Evaluation Board For AD9238 Dual A/D Converter ,12-Bit, 20 MSPS/40 MSPS/65 MSPS 制造商:Rochester Electronics LLC 功能描述:DUAL 12 BIT 3V CMOS 20/40/65 MSPS ADC - Bulk |
| AD9238BST-65PCBZ | 制造商:Analog Devices 功能描述:DUAL 12 BIT 3V CMOS 20/40/65 MSPS ADC - Bulk |
| AD9238BSTRL-20 | 制造商:Rochester Electronics LLC 功能描述:DUAL 12 BIT 3V CMOS 20/40/65 MSPS ADC - Bulk 制造商:Analog Devices 功能描述: |
| AD9238BSTRL-40 | 功能描述:IC ADC 12BIT DUAL 40MSPS 64-LQFP RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 位數(shù):12 采樣率（每秒）:3M 數(shù)據(jù)接口:- 轉(zhuǎn)換器數(shù)目:- 功率耗散（最大）:- 電壓電源:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:SOT-23-6 供應(yīng)商設(shè)備封裝:SOT-23-6 包裝:帶卷 (TR) 輸入數(shù)目和類型:- |
| AD9238BSTRL-65 | 功能描述:IC ADC 12BIT DUAL 65MSPS 64-LQFP RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 位數(shù):12 采樣率（每秒）:3M 數(shù)據(jù)接口:- 轉(zhuǎn)換器數(shù)目:- 功率耗散（最大）:- 電壓電源:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:SOT-23-6 供應(yīng)商設(shè)備封裝:SOT-23-6 包裝:帶卷 (TR) 輸入數(shù)目和類型:- |
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