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參數(shù)資料
| 型號(hào)： | AD9229ABCPZRL7-65 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 18/40頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 12BIT SRL 65MSPS 48LFCSP |
| 標(biāo)準(zhǔn)包裝： | 750 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 65M |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 4 |
| 功率耗散（最大）： | 1.47W |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 48-LFCSP-VQ（7x7） |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 8 個(gè)單端，單極；4 個(gè)差分，單極 |
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AD9229
Rev. B | Page 25 of 40
DEFAULT OPERATION AND JUMPER SELECTION
SETTINGS
The following is a list of the default and optional settings or
modes allowed on the AD9229 Rev C evaluation board.
POWER: Connect the switching power supply that is
supplied in the evaluation kit between a rated 100 V to
240 V ac wall outlet at 47 Hz to 63 Hz and P503.
AIN: The evaluation board is set up for a transformer
coupled analog input with optimum 50 Ω impedance
matching out to 400 MHz. For more bandwidth response,
the 2.2 pF differential capacitor across the analog inputs
could be changed or removed. The common mode of the
analog inputs is developed from the center tap of the
transformer or AVDD_DUT/2.
VREF: VREF is set to 1.0 V by tying the SENSE pin to
ground, R224. This causes the ADC to operate in 2.0 V p-p
full-scale range. A number of other VREF options are
available on the evaluation board, including 1.0 V p-p full-
scale range, a variable range that the user can set by
choosing R219 and R220 as well as a separate external
reference option using the ADR510 or ADR520. Simply
populate R218 and R222 and remove C208. To use these
optional VREF modes, switch the jumper setting on R221
to R224. Proper use of the VREF options is noted in the
Voltage Reference section.
CLOCK: The clock input circuitry is derived from a simple
logic circuit using a high speed inverter that adds a very
low amount of jitter to the clock path. The clock input is
50 Ω terminated and ac-coupled to handle sine wave
type inputs. If using an oscillator, two oscillator footprint
options are also available (OSC200-201) to check the
ADC’s performance. J203 and J204 give the user flexibility
in using the enable pin, which is common on most
oscillators.
PWDN: To enable the power-down feature, simply short
JP201 to AVDD on the PWDN pin.
DTP: To enable one of the two digital test patterns on
digital outputs of the ADC, use JP202. If Pins 2 and 3 on
JP202 are tied together (1.0 V source), this enables test
pattern 1000 0000 0000. If Pins 1 and 2 on JP202 are tied
together (2.0 V source), this enables test pattern 1010 1010
1010. See the DTP Pin section for more details.
LVDSBIAS: To change the level of the LVDS output level
swing, simply change the value of R204. Other recom-
mended values can be found in the Digital Outputs
section.
D+, D–: If an alternate data capture method to the setup
described in Figure 47 is used, optional receiver
terminations, R205 to R210, can be installed next to the
high speed backplane connector.
ALTERNATE ANALOG INPUT DRIVE
CONFIGURATION
The following is a brief description of the alternate analog input
drive configuration using the AD8332 dual VGA. This parti-
cular drive option may need to be populated, in which case all
the necessary components are listed in Table 11. This table lists
the necessary settings to properly configure the evaluation
board for this option. For more details on the AD8332 dual
VGA, how it works, and its optional pin settings, consult the
AD8332 data sheet.
To configure the analog input to drive the VGA instead of the
default transformer option, the following components need to
be removed and/or changed.
1.
Remove R102, R115, R128, R141, T101, T102, T103, and
T1044 in the default analog input path.
2.
Populate R101, R114, R127, and R140 with 0 Ω resistors in
the analog input path.
3.
Populate R106, R107, R119, R120, R132, R133, R144, and
R145 with 10 kΩ resistors to provide an input common-
mode level to the analog input.
4.
Populate R105, R113, R118, R124, R131, R137, R151, and
R43 with 0 Ω resistors in the analog input path.
5.
Currently L305 to L312 and L405 to L412 are populated
with 0 Ω resistors to allow signal connection. This area
allows the user to design a filter if additional requirements
are necessary.
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