參數(shù)資料
型號(hào)： AD9226ARS
廠商： ANALOG DEVICES INC
元件分類(lèi)： ADC
英文描述： Complete 12-Bit, 65 MSPS ADC Converter
中文描述： 1-CH 12-BIT FLASH METHOD ADC, PARALLEL ACCESS, PDSO28
封裝： SSOP-28
文件頁(yè)數(shù)： 18/28頁(yè)
文件大?。?/td> 1480K
代理商： AD9226ARS
REV. 0
AD9226
–18–
A2
LOGIC
A1
DISABLE
A1
1V
TO
A/D
AD9226
CAPT
CAPB
VREF
SENSE
REFCOM
2.5V
Figure 11a. Equivalent Reference Circuit
0.1 F
10 F
0.1 F
0.1 F
CAPT
CAPB
AD9226
VREF
0.1 F
10 F
Figure 11b. CAPT and CAPB DC-Coupling
The actual reference voltages used by the internal circuitry of the
AD9226 appear on the CAPT and CAPB pins. The voltages
on these pins are symmetrical about the analog supply. For
proper operation when using an internal or external reference, it
is necessary to add a capacitor network to decouple these pins.
Figure 11b shows the recommended decoupling network. The
turn-on time of the reference voltage appearing between CAPT
and CAPB is approximately 10 ms and should be evaluated in
any power-down mode of operation.
USING THE INTERNAL REFERENCE
The AD9226 can be easily configured for either a 1 V p-p input
span or 2 V p-p input span by setting the internal reference.
Other input spans can be realized with two external gain-
setting resistors as shown in Figure 12 of this data sheet, or
using an external reference.
Pin Programmable Reference
By shorting the VREF pin directly to the SENSE pin, the inter-
nal reference amplifier is placed in a unity-gain mode and the
resultant VREF output is 1 V. By shorting the SENSE pin
directly to the REFCOM pin, the internal reference amplifier is
configured for a gain of 2.0 and the resultant VREF output is
2.0 V. The VREF pin should be bypassed to the REFCOM pin
with a 10
μ
F tantalum capacitor in parallel with a low-inductance
0.1
μ
F ceramic capacitor as shown in Figure 11b.
Resistor Programmable Reference
Figure 12 shows an example of how to generate a reference
voltage other than 1.0 V or 2.0 V with the addition of two exter-
nal resistors. Use the equation,
VREF
= 1
V
×
(1 +
R
1/
R
2)
to determine appropriate values for
R
1 and
R
2. These resistors
should be in the 2 k
to 10 k
range. For the example shown,
R1 equals 2.5 k
and R2 equals 5 k
. From the equation above,
the resultant reference voltage on the VREF pin is 1.5 V. This
sets the input span to be 1.5 V p-p. The midscale voltage can
also be set to VREF by connecting VINB to VREF. Alterna-
tively, the midscale voltage can be set to 2.5 V by connecting
VINB to a low-impedance 2.5 V source as shown in Figure 12.
VINA
VREF
AD9226
VINB
1.75V
SENSE
REFCOM
0.1 F
10 F
0.1 F
0.1 F
15pF
3.25V
33
33
1.5V
0.1 F
CAPT
2.5V
10 F
R1
2.5k
R2
5k
CAPB
0.1C1
Figure 12. Resistor Programmable Reference (1.5 V p-p
Input Span, Differential Input V
CM
= 2.5 V)
USING AN EXTERNAL REFERENCE
The AD9226 contains an internal reference buffer, A2 (see
Figure 11b), that simplifies the drive requirements of an external
reference. The external reference must be able to drive about
5 k
(
±
20%) load. Note that the bandwidth of the reference
buffer is deliberately left small to minimize the reference noise
contribution. As a result, it is not possible to rapidly change the
reference voltage in this mode.
Figure 13 shows an example of an external reference driving
both VINB and VREF. In this case, both the common-mode
voltage and input span are directly dependent on the value of
VREF. Both the input span and the center of the input span are
equal to the external VREF. Thus the valid input range extends
from (VREF + VREF/2) to (VREF
–
VREF/2). For example,
if the REF191, a 2.048 V external reference, is selected, the
input span extends to 2.048 V. In this case, 1 LSB of the AD9226
corresponds to 0.5 mV. It is essential that a minimum of a 10
μ
F
capacitor, in parallel with a 0.1
μ
F low-inductance ceramic
capacitor, decouple the reference output to ground.
To use an external reference, the SENSE pin must be connected
to AVDD. This connection will disable the internal reference.
VINA
VREF
AD9226
VINB
SENSE
0.1 F
10 F
0.1 F
0.1 F
15pF
VINA+VREF/2
33
33
0.1 F
CAPT
CAPB
VINB
–
VREF/2
10 F
VREF
0.1 F
5V
5V
Figure 13. Using an External Reference
MODE CONTROLS
Clock Stabilizer
The clock stabilizer is a circuit that desensitizes the ADC from
clock duty cycle variations. The AD9226 eases system clock
constraints by incorporating a circuit that restores the internal duty
cycle to 50%, independent of the input duty cycle. Low jitter on
the rising edge (sampling edge) of the clock is preserved while
the noncritical falling edge is generated on-chip.
It may be desirable to disable the clock stabilizer, and may be
necessary when the clock frequency speed is varied or completely
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