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參數(shù)資料
| 型號(hào)： | AD9220ARZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 28/32頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 12BIT 10MSPS 28-SOIC |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 10M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 7 |
| 功率耗散（最大）： | 310mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 28-SOIC W |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 2 個(gè)單端，單極；1 個(gè)差分，單極 |
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REV. E
AD9221/AD9223/AD9220
–5–
PIN CONFIGURATION
14
13
12
11
17
16
15
20
19
18
10
9
8
1
2
3
4
7
6
5
TOP VIEW
(Not to Scale)
28
27
26
25
24
23
22
21
AD9221/
AD9223/
AD9220
CLK
AVSS
AVDD
DVSS
DVDD
(LSB) BIT 12
BIT 11
BIT 10
CML
VINA
VINB
BIT 9
BIT 8
BIT 7
BIT 6
BIT 5
BIT 4
REFCOM
CAPB
CAPT
BIT 3
BIT 2
(MSB) BIT 1
OTR
VREF
AVDD
AVSS
SENSE
PIN FUNCTION DESCRIPTIONS
Pin
Number
Mnemonic
Description
1
CLK
Clock Input Pin
2BIT 12
Least Significant Data Bit (LSB)
3–12
BITS 11–2
Data Output Bit
13
BIT 1
Most Significant Data Bit (MSB)
14
OTR
Out of Range
15, 26
AVDD
5 V Analog Supply
16, 25
AVSS
Analog Ground
17
SENSE
Reference Select
18
VREF
Reference I/O
19
REFCOM
Reference Common
20
CAPB
Noise Reduction Pin
21
CAPT
Noise Reduction Pin
22
CML
Common-Mode Level (Midsupply)
23
VINA
Analog Input Pin (+)
24
VINB
Analog Input Pin (–)
27
DVSS
Digital Ground
28
DVDD
3 V to 5 V Digital Supply
DEFINITIONS OF SPECIFICATIONS
Integral Nonlinearity (INL)
INL refers to the deviation of each individual code from a line
drawn from “negative full scale” through “positive full scale.”
The point used as negative full scale occurs 1/2 LSB before the
first code transition. Positive full scale is defined as a level 1 1/2
LSB beyond the last code transition. The deviation is measured
from the middle of each particular code to the true straight line.
Differential Nonlinearity (DNL, No Missing Codes)
An ideal ADC exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value. Guaranteed
no missing codes to 12-bit resolution indicates that all 4096
codes, respectively, must be present over all operating ranges.
Zero Error
The major carry transition should occur for an analog value 1/2
LSB below VINA = VINB. Zero error is defined as the devia-
tion of the actual transition from that point.
Gain Error
The first code transition should occur at an analog value 1/2 LSB
above negative full scale. The last transition should occur at an
analog value 1 1/2 LSB below the nominal full scale. Gain error
is the deviation of the actual difference between first and last
code transitions and the ideal difference between first and last
code transitions.
Temperature Drift
The temperature drift for zero error and gain error specifies the
maximum change from the initial (25
°C) value to the value at
TMIN or TMAX.
Power Supply Rejection
The specification shows the maximum change in full scale from
the value with the supply at the minimum limit to the value with
the supply at its maximum limit.
Aperture Jitter
Aperture jitter is the variation in aperture delay for successive
samples and is manifested as noise on the input to the A/D.
Aperture Delay
Aperture delay is a measure of the sample-and-hold amplifier
(SHA) performance and is measured from the rising edge of the
clock input to when the input signal is held for conversion.
Signal-to-Noise and Distortion (S/N+D, SINAD) Ratio
S/N+D is the ratio of the rms value of the measured input signal
to the rms sum of all other spectral components below the Nyquist
frequency, including harmonics but excluding dc. The value for
S/N+D is expressed in decibels.
Effective Number of Bits (ENOB)
For a sine wave, SINAD can be expressed in terms of the num-
ber of bits. Using the following formula,
N
SINAD
=
()
–.
/ .
176
6 02
it is possible to get a measure of performance expressed as N,
the effective number of bits.
Thus, effective number of bits for a device for sine wave inputs
at a given input frequency can be calculated directly from its
measured SINAD.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of the first six harmonic com-
ponents to the rms value of the measured input signal and is
expressed as a percentage or in decibels.
Signal-to-Noise Ratio (SNR)
SNR is the ratio of the rms value of the measured input signal to
the rms sum of all other spectral components below the Nyquist
frequency, excluding the first six harmonics and dc. The value
for SNR is expressed in decibels.
Spurious Free Dynamic Range (SFDR)
SFDR is the difference in dB between the rms amplitude of the
input signal and the peak spurious signal.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9220-EB | 制造商:Analog Devices 功能描述:EVAL KIT FOR COMPLETE 12-BIT 1.5/3.0/10.0MSPS MONOLITHIC A/D - Bulk |
| AD9221 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Complete 12-Bit 1.5/3.0/10.0 MSPS Monolithic A/D Converters |
| AD9221AR | 功能描述:IC ADC 12BIT 1.5MSPS 28-SOIC RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 位數(shù):12 采樣率（每秒）:300k 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:75mW 電壓電源:單電源 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:24-SOIC 包裝:帶卷 (TR) 輸入數(shù)目和類型:1 個(gè)單端，單極；1 個(gè)單端，雙極 |
| AD9221AR-REEL | 功能描述:IC ADC 12BIT 1.5MSPS 28-SOIC RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 位數(shù):12 采樣率（每秒）:300k 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:75mW 電壓電源:單電源 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:24-SOIC 包裝:帶卷 (TR) 輸入數(shù)目和類型:1 個(gè)單端，單極；1 個(gè)單端，雙極 |
| AD9221ARS | 功能描述:IC ADC 12BIT 1.5MSPS 28-SSOP RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 位數(shù):12 采樣率（每秒）:300k 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:75mW 電壓電源:單電源 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:24-SOIC 包裝:帶卷 (TR) 輸入數(shù)目和類型:1 個(gè)單端，單極；1 個(gè)單端，雙極 |
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