參數(shù)資料
型號(hào)： AD9220ARZ-REEL
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 14/32頁(yè)
文件大?。?/td> 0K
描述： IC ADC 12BIT 10MSPS 28-SOIC
標(biāo)準(zhǔn)包裝： 1,000
位數(shù)： 12
采樣率（每秒）： 10M
數(shù)據(jù)接口： 并聯(lián)
轉(zhuǎn)換器數(shù)目： 7
功率耗散（最大）： 310mW
電壓電源： 單電源
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 28-SOIC（0.295"，7.50mm 寬）
供應(yīng)商設(shè)備封裝： 28-SOIC W
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 2 個(gè)單端，單極；1 個(gè)差分，單極
REV. E
AD9221/AD9223/AD9220
–21–
can be detected. Table V is a truth table for the over/underrange
circuit in Figure 28, which uses NAND gates. Systems requiring
programmable gain conditioning of the AD9221/AD9223/
AD9220 input signal can immediately detect an out-of-range
condition, thus eliminating gain selection iterations. Also, OTR
can be used for digital offset and gain calibration.
Table V. Out-of-Range Truth Table
OTR
MSB
Analog Input Is
00
In Range
01
In Range
10
Underrange
11
Overrange
OVER = “1”
UNDER = “1”
MSB
OTR
MSB
Figure 28. Overrange or Underrange Logic
Digital Output Driver Considerations (DVDD)
The AD9221, AD9223 and AD9220 output drivers can be
configured to interface with 5 V or 3.3 V logic families by setting
DVDD to 5 V or 3.3 V respectively. The AD9221/AD9223/
AD9220 output drivers are sized to provide sufficient output
current to drive a wide variety of logic families. However, large
drive currents tend to cause glitches on the supplies and may
affect SINAD performance. Applications requiring the AD9221/
AD9223/AD9220 to drive large capacitive loads or large fanout
may require additional decoupling capacitors on DVDD. In
extreme cases, external buffers or latches may be required.
Clock Input and Considerations
The AD9221/AD9223/AD9220 internal timing uses the two
edges of the clock input to generate a variety of internal timing
signals. The clock input must meet or exceed the minimum
specified pulsewidth high and low (tCH and tCL) specifications
for the given A/D as defined in the Switching Specifications to
meet the rated performance specifications. For example, the
clock input to the AD9220 operating at 10 MSPS may have a
duty cycle between 45% to 55% to meet this timing requirement
since the minimum specified tCH and tCL is 45 ns. For clock
rates below 10 MSPS, the duty cycle may deviate from this
range to the extent that both tCH and tCL are satisfied.
All high speed high resolution A/Ds are sensitive to the quality
of the clock input. The degradation in SNR at a given full-scale
input frequency (fIN) due to only aperture jitter (tA) can be
calculated with the following equation:
SNR
f
t
IN
A
=
[]
20
1 2
10
log
/
π
In the equation, the rms aperture jitter, tA, represents the root-
sum square of all the jitter sources, which include the clock
input, analog input signal, and A/D aperture jitter specification.
For example, if a 5 MHz full-scale sine wave is sampled by an
A/D with a total rms jitter of 15 ps, the SNR performance of the
A/D will be limited to 66.5 dB. Undersampling applications are
particularly sensitive to jitter.
The clock input should be treated as an analog signal in cases
where aperture jitter may affect the dynamic range of the AD9221/
AD9223/AD9220. As such, supplies for clock drivers should be
separated from the A/D output driver supplies to avoid modulating
the clock signal with digital noise. Low jitter crystal controlled
oscillators make the best clock sources. If the clock is generated
from another type of source (by gating, dividing, or other method),
it should be retimed by the original clock at the last step.
Most of the power dissipated by the AD9221/AD9223/AD9220
is from the analog power supplies. However, lower clock speeds
will reduce digital current slightly. Figure 29 shows the relation-
ship between power and clock rate for each A/D.
CLOCK FREQUENCY – MHz
66
64
56
3.0
POWER
–
mW
2.5
62
60
58
5V p-p
2V p-p
54
52
50
48
2.0
1.5
1.0
0.5
Figure 29a. AD9221 Power Consumption vs. Clock
Frequency
CLOCK FREQUENCY – MHz
125
120
105
6
POWER
–
mW
5
115
110
5V p-p
2V p-p
100
95
90
4
3
2
1
0
Figure 29b. AD9223 Power Consumption vs. Clock
Frequency
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD9220-EB 制造商:Analog Devices 功能描述:EVAL KIT FOR COMPLETE 12-BIT 1.5/3.0/10.0MSPS MONOLITHIC A/D - Bulk
AD9221 制造商:AD 制造商全稱:Analog Devices 功能描述:Complete 12-Bit 1.5/3.0/10.0 MSPS Monolithic A/D Converters
AD9221AR 功能描述:IC ADC 12BIT 1.5MSPS 28-SOIC RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 位數(shù):12 采樣率（每秒）:300k 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:75mW 電壓電源:單電源 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:24-SOIC 包裝:帶卷 (TR) 輸入數(shù)目和類型:1 個(gè)單端，單極；1 個(gè)單端，雙極
AD9221AR-REEL 功能描述:IC ADC 12BIT 1.5MSPS 28-SOIC RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 位數(shù):12 采樣率（每秒）:300k 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:75mW 電壓電源:單電源 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:24-SOIC 包裝:帶卷 (TR) 輸入數(shù)目和類型:1 個(gè)單端，單極；1 個(gè)單端，雙極
AD9221ARS 功能描述:IC ADC 12BIT 1.5MSPS 28-SSOP RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 位數(shù):12 采樣率（每秒）:300k 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:75mW 電壓電源:單電源 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:24-SOIC 包裝:帶卷 (TR) 輸入數(shù)目和類型:1 個(gè)單端，單極；1 個(gè)單端，雙極
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