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參數(shù)資料
| 型號(hào)： | AD9219ABCPZRL7-40 |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 28/56頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 10BIT SRL 40MSPS 64LFCSP |
| 標(biāo)準(zhǔn)包裝： | 750 |
| 位數(shù)： | 10 |
| 采樣率（每秒）： | 40M |
| 數(shù)據(jù)接口： | 串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 4 |
| 功率耗散（最大）： | 313mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-VFQFN 裸露焊盤(pán)，CSP |
| 供應(yīng)商設(shè)備封裝： | 48-LFCSP-VQ（7x7） |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 8 個(gè)單端，單極；4 個(gè)差分，單極 |
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AD9219
Data Sheet
Rev. E | Page 34 of 56
Table 16. Memory Map Register
Addr.
(Hex)
Register Name
(MSB)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
(LSB)
Bit 0
Default
Value
(Hex)
Default Notes/
Comments
Chip Configuration Registers
00
chip_port_config
0
LSB first
1 = on
0 = off
(default)
Soft
reset
1 = on
0 = off
(default)
1
Soft
reset
1 = on
0 = off
(default)
LSB first
1 = on
0 = off
(default)
0
0x18
The nibbles
should be
mirrored so that
LSB- or MSB-first
mode is set cor-
rectly regardless
of shift mode.
01
chip_id
8-bit Chip ID Bits [7:0]
(AD9219 = 0x03), (default)
0x02
Default is unique
chip ID, different
for each device.
This is a read-
only register.
02
chip_grade
X
Child ID [6:4]
(identify device variants of Chip ID)
000 = 65 MSPS
001 = 40 MSPS
X
Read
only
Child ID used to
differentiate
graded devices.
Device Index and Transfer Registers
05
device_index_A
X
Clock
Channel
DCO
1 = on
0 = off
(default)
Clock
Channel
FCO
1 = on
0 = off
(default)
Data
Channel
D
1 = on
(default)
0 = off
Data
Channel
C
1 = on
(default)
0 = off
Data
Channel
B
1 = on
(default)
0 = off
Data
Channel
A
1 = on
(default)
0 = off
0x0F
Bits are set to
determine which
on-chip device
receives the next
write command.
FF
device_update
X
SW
transfer
1 = on
0 = off
(default)
0x00
Synchronously
transfers data
from the master
shift register to
the slave.
ADC Functions
08
modes
X
Internal power-down mode
000 = chip run (default)
001 = full power-down
010 = standby
011 = reset
0x00
Determines
various generic
modes of chip
operation.
09
clock
X
Duty
cycle
stabilizer
1 = on
(default)
0 = off
0x01
Turns the
internal duty
cycle stabilizer
on and off.
0D
test_io
User test mode
00 = off (default)
01 = on, single alternate
10 = on, single once
11 = on, alternate once
Reset PN
long gen
1 = on
0 = off
(default)
Reset
PN short
gen
1 = on
0 = off
(default)
Output test mode—see
Table 9 in the Digital
Outputs and Timing section.
0000 = off (default)
0001 = midscale short
0010 = +FS short
0011 = FS short
0100 = checkerboard output
0101 = PN 23 sequence
0110 = PN 9 sequence
0111 = one-/zero-word toggle
1000 = user input
1001 = 1-/0-bit toggle
1010 = 1× sync
1011 = one bit high
1100 = mixed bit frequency
(format determined by output_mode)
0x00
When this reg-
ister is set, the
test data is placed
on the output
pins in place of
normal data.
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| AD9219ABCPZRL7-65 | 功能描述:IC ADC 10BIT SRL 65MSPS 64LFCSP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 位數(shù):12 采樣率（每秒）:300k 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:75mW 電壓電源:單電源 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:24-SOIC 包裝:帶卷 (TR) 輸入數(shù)目和類型:1 個(gè)單端，單極；1 個(gè)單端，雙極 |
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