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參數(shù)資料
| 型號： | AD9117-DPG2-EBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 6/52頁 |
| 文件大小： | 0K |
| 描述： | IC DAC DUAL 14BIT LO PWR 40LFCSP |
| 標準包裝： | 1 |
| 系列： | TxDAC® |
| DAC 的數(shù)量： | 2 |
| 位數(shù)： | 14 |
| 采樣率（每秒）： | 125M |
| 數(shù)據(jù)接口： | 串行 |
| DAC 型： | 電流 |
| 工作溫度： | -40°C ~ 85°C |
| 已供物品： | 板 |
| 已用 IC / 零件： | AD9117 |
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AD9114/AD9115/AD9116/AD9117
Data Sheet
Rev. C | Page 14 of 52
PIN 1
INDICATOR
1
DB9
2
DB8
3
DB7
4
DB6
5
DVDDIO
6
DVSS
7
DVDD
8
DB5
9
DB4
10
DB3
23 QOUTP
24 RLQP
25 AVSS
26 AVDD
27 RLIP
28 IOUTP
29 IOUTN
30 RLIN
22 QOUTN
21 RLQN
1
DB2
12
DB1
13
DB0
(
L
S
B)
15
NC
17
CV
DD
16
DCL
KI
O
18
CL
KI
N
19
C
VSS
20
CM
L
Q
14
NC
33
F
S
ADJI
/AUX
I
34
R
E
FIO
35
R
ESET
/PI
N
MD
36
S
CL
K/
CL
KM
D
37
S
D
IO/FOR
M
A
T
38
CS
/P
W
RDN
39
DB
1
(MSB
)
40
DB10
32
F
S
ADJQ
/AUX
Q
31
CM
L
I
TOP VIEW
(Not to Scale)
AD9116
NOTES
1. NC = NO CONNECT
2. THE EXPOSED PAD IS CONNECTED TO AVSS AND
MUST BE SOLDERED TO THE GROUND PLANE.
EXPOSED METAL AT PACKAGE CORNERS IS
CONNECTED TO THIS PAD.
07466-
003
Figure 4. AD9116 Pin Configuration
Table 9. AD9116 Pin Function Descriptions
Pin No.
Mnemonic
Description
1 to 4
DB[9:6]
Digital Inputs.
5
DVDDIO
Digital I/O Supply Voltage Input (1.8 V to 3.3 V Nominal).
6
DVSS
Digital Common.
7
DVDD
Digital Core Supply Voltage Output (1.8 V). Strap DVDD to DVDDIO at 1.8 V. If DVDDIO > 1.8 V, bypass DVDD
with a 1.0 F capacitor; however, do not otherwise connect it. The LDO should not drive external loads.
8 to 12
DB[5:1]
Digital Inputs.
13
DB0 (LSB)
Digital Input (LSB).
14, 15
NC
No Connect. These pins are not connected to the chip.
16
DCLKIO
Data Input/Output Clock. Clock used to qualify input data.
17
CVDD
Sampling Clock Supply Voltage Input (1.8 V to 3.3 V). CVDD must be ≥ DVDD.
18
CLKIN
LVCMOS Sampling Clock Input.
19
CVSS
Sampling Clock Supply Voltage Common.
20
CMLQ
Q DAC Output Common-Mode Level. When the internal on-chip (QRCML) is enabled, this pin is connected to
the on-chip QRCML resistor. It is recommended to leave this pin unconnected. When the internal on-chip (QRCML) is
disabled, this pin is the common-mode load for Q DAC and must be connected to AVSS through a resistor,
see the Using the Internal Termination Resistors section. Recommended value for this external resistor is 0 .
21
RLQN
Load Resistor (62.5 ) to the CMLQ Pin. For the internal load resistor to be used, this pin should be tied to
QOUTN externally.
22
QOUTN
Complementary Q DAC Current Output. Full-scale current is sourced when all data bits are 0s.
23
QOUTP
Q DAC Current Output. Full-scale current is sourced when all data bits are 1s.
24
RLQP
Load Resistor (62.5 ) to the CMLQ Pin. For the internal load resistor to be used, this pin should be tied to
QOUTP externally.
25
AVSS
Analog Common.
26
AVDD
Analog Supply Voltage Input (1.8 V to 3.3 V).
27
RLIP
Load Resistor (62.5 ) to the CMLI Pin. For the internal load resistor to be used, this pin should be tied to
IOUTP externally.
28
IOUTP
I DAC Current Output. Full-scale current is sourced when all data bits are 1s.
29
IOUTN
Complementary I DAC Current Output. Full-scale current is sourced when all data bits are 0s.
30
RLIN
Load Resistor (62.5 ) to the CMLI Pin. For the internal load resistor to be used, this pin should be tied to
IOUTN externally.
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