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參數(shù)資料
| 型號： | AD9116BCPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 41/52頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC DUAL 12BIT LO PWR 40LFCSP |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 標準包裝： | 1 |
| 系列： | TxDAC® |
| 位數(shù)： | 12 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 電壓電源： | 模擬和數(shù)字 |
| 功率耗散（最大）： | 232mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 40-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 40-LFCSP-VQ（6x6） |
| 包裝： | 托盤 |
| 輸出數(shù)目和類型： | 4 電流，單極 |
| 采樣率（每秒）： | 125M |
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AD9114/AD9115/AD9116/AD9117
Data Sheet
Rev. C | Page 46 of 52
REFIO pin. Noise injected here appears as amplitude modulation
of the output; therefore, a portion of the required series resistance
(at least 10 kΩ) must be installed at the pin. A range of ±25% is
quite practical when using this method.
Fine Gain
Each main DAC has independent fine gain control using the
lower six bits in Register 0x03 (I DACGAIN[5:0]) and Register
0x06 (Q DACGAIN[5:0]). Unlike Coarse Gain Option 1, this
impacts only the main DAC full-scale output current. These
registers use straight binary format. One application in which
straight binary format is critical is for side-band suppression
while using a quadrature modulator. This is described in more
detail in the Applications Information section.
11.10
11.00
10.90
10.80
10.70
10.60
10.50
0
8
16
24
32
40
48
56
64
GAIN DAC CODE
I O
U
TFS
(
mA)
3.3V DAC1
3.3V DAC2
1.8V DAC1
1.8V DAC2
07466-
060
Figure 99. Typical DAC Gain Characteristics
USING THE INTERNAL TERMINATION RESISTORS
The AD9117/AD9116/AD9115/AD9114 have four 62.5 Ω
termination internal resistors (two for each DAC output).
To use these resistors to convert the DAC output current to a
voltage, connect each DAC output pin to the adjacent load pin.
For example, on the I DAC, IOUTP must be shorted to RLIP
and IOUTN must be shorted to RLIN. In addition, the CMLI
or CMLQ pin must be connected to ground directly or through
a resistor. If the output current is at the nominal 20 mA and the
CMLI or CMLQ pin is tied directly to ground, this produces a
dc common-mode bias voltage on the DAC output equal to
0.625 V. If the DAC dc bias must be higher than 0.625 V, an
external resistor can be connected between the CMLI or CMLQ
pin and ground. This part also has an internal common-mode
resistor that can be enabled. This is explained in the Using the
Internal Common-Mode Resistor section.
I DAC
OR
Q DAC
xRCM
CML
RLIN
IOUTN
IOUTP
RLIP
62.5
07466-
061
Figure 100. Simplified Internal Load Options
Using the Internal Common-Mode Resistor
These devices contain an adjustable internal common-mode
resistor that can be used to increase the dc bias of the DAC
outputs. By default, the common-mode resistor is not connected.
When enabled, it can be adjusted from ~60 Ω to ~260 Ω. Each
main DAC has an independent adjustment using the lower six bits
in Register 0x05 (IRCML[5:0]) and Register 0x08 (QRCML[5:0]).
260
220
240
200
180
160
140
120
100
80
60
0
8
16
24
32
40
48
56
CODE
R
ESI
ST
A
N
C
E
(
)
07466-
062
Figure 101. Typical CML Resistor Value vs. Register Code
Using the CMLx Pins for Optimal Performance
The CMLx pins also serve to change the DAC bias voltages in
the parts allowing them to run at higher dc output bias voltages.
When running the bias voltage below 0.9 V and an AVDD of
3.3 V, the parts perform optimally when the CMLx pins are tied
to ground. When the dc bias increases above 0.9 V, set the CMLx
pins at 0.5 V for optimal performance. The maximum dc bias
on the DAC output should be kept at or below 1.2 V when the
supply is 3.3 V. When the supply is 1.8 V, keep the dc bias close
to 0 V and connect the CMLx pins directly to ground.
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參數(shù)描述 |
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| AD9116BCPZRL7 | 功能描述:IC DAC DUAL 12BIT LO PWR 40LFCSP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:TxDAC® 標準包裝:47 系列:- 設(shè)置時間:2µs 位數(shù):14 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 電壓電源:單電源 功率耗散（最大）:55µW 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:管件 輸出數(shù)目和類型:1 電流，單極；1 電流，雙極 采樣率（每秒）:* |
| AD9116-DPG2-EBZ | 功能描述:IC DAC DUAL 12BIT LO PWR 40LFCSP RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估板 - 數(shù)模轉(zhuǎn)換器 (DAC) 系列:TxDAC® 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1 系列:- DAC 的數(shù)量:4 位數(shù):12 采樣率（每秒）:- 數(shù)據(jù)接口:串行，SPI? 設(shè)置時間:3µs DAC 型:電流/電壓 工作溫度:-40°C ~ 85°C 已供物品:板 已用 IC / 零件:MAX5581 |
| AD9116-EBZ | 制造商:Analog Devices 功能描述:DUAL 12 BIT LOW POWER CONVERTER - Boxed Product (Development Kits) |
| AD9117 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual, 8-/10-/12-/14-Bit Low Power Digital-to-Analog Converters |
| AD9117BCPZ | 功能描述:IC DAC DUAL 14BIT LO PWR 40LFCSP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:TxDAC® 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:50 系列:- 設(shè)置時間:4µs 位數(shù):12 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:2 電壓電源:單電源 功率耗散（最大）:- 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:8-TSSOP，8-MSOP（0.118"，3.00mm 寬） 供應(yīng)商設(shè)備封裝:8-uMAX 包裝:管件 輸出數(shù)目和類型:2 電壓，單極 采樣率（每秒）:* 產(chǎn)品目錄頁面:1398 (CN2011-ZH PDF) |
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