R
參數資料
型號: AD8555ARZ
廠商: Analog Devices Inc
文件頁數: 19/28頁
文件大小: 0K
描述: IC AMP CHOPPER 2MHZ 10MA 8SOIC
標準包裝: 98
系列: DigiTrim®
放大器類型: 斷路器(零漂移)
電路數: 1
轉換速率: 1.2 V/µs
增益帶寬積: 2MHz
電流 - 輸入偏壓: 16nA
電壓 - 輸入偏移: 2µV
電流 - 電源: 2mA
電流 - 輸出 / 通道: 10mA
電壓 - 電源,單路/雙路(±): 2.7 V ~ 5.5 V
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 8-SOIC(0.154",3.90mm 寬)
供應商設備封裝: 8-SO
包裝: 管件
產品目錄頁面: 771 (CN2011-ZH PDF)
AD8555
Rev. A | Page 26 of 28
04598-0-029
LOAD CAPACITANCE (nF)
100.0
0.1
1.0
10.0
OVER
SH
OOT
(
%
)
60
50
40
30
20
10
0
RS
CL
VS = ±2.5V
RS = 0
RS = 10
RS = 20
RS = 50
RS = 100
Figure 58. Negative Overshoot Graph vs. CL
RF INTERFERENCE
All instrumentation amplifiers show dc offset as the result of
rectification of high frequency out-of-band signals that appear
at their inputs. The circuit in Figure 59 provides good RFI sup-
pression without reducing performance within the AD8555
pass band. Resistor R1 and Capacitor C1, and likewise Resistor
R2 and Capacitor C2, form a low-pass RC filter that has a 3 dB
bandwidth equal to f(3 dB) = 1/2 π × R1 × C1. It can be seen that
R1, R2 and C1, C2 form a bridge circuit whose output appears
across the amplifier’s input pins. Any mismatch between C1, C2
unbalances the bridge and reduce the common-mode rejection.
Using the component values shown, this filter has a bandwidth
of approximately 40 kHz. To preserve common-mode rejection
in the AD8555’s pass band, capacitors need to be 5% (silver
mica) or better and should be placed as close to its inputs as
possible. Resistors should be 1% metal film. Capacitor C3 is
needed to maintain common-mode rejection at low frequen-
cies. This introduces a second low-pass network, R1 + R2 and
C3 that has a 3 dB frequency equal to 1/(2 π × (R1 + R2)(C3)).
This circuit’s 3 dB signal bandwidth is approximately 4 kHz
when a C3 value of 0.047 μF is used (see Figure 59).
1
2
3
4
5
6
7
8
AD8555
VDD
FILT/DIGOUT
DIGIN
VNEG
VSS
VOUT
VCLAMP
VPOS
VDD
VSS
04598-0-057
VNEG
R2
4.02k
Ω
R1
4.02k
Ω
C3
0.047
μF
C2
1nF
C1
1nF
Figure 59. RFI Suppression Method
SINGLE-SUPPLY DATA ACQUISITION SYSTEM
Interfacing bipolar signals to single-supply analog-to-digital
converters (ADCs) presents a challenge. The bipolar signal
must be mapped into the input range of the ADC. Figure 60
shows how this translation can be achieved. The output offset
can be programmed to a desirable level to accommodate the
input voltage requirement of the ADC.
1
2
3
4
5
6
7
8
AD8555
VDD
FILT/DIGOUT
DIGIN
VNEG
2
4
AD7476
12 BIT
AIN
VDD
VSS
VOUT
VCLAMP
VPOS
VDD
04598-0-058
VDD
SDIGIN
10nF
0
100
Ω
100
Ω
100
Ω
100
Ω
Figure 60. A Single-Supply Data Acquisition Circuit Using the AD8555
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