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參數(shù)資料
| 型號(hào)： | AD842 |
| 廠(chǎng)商： | Analog Devices, Inc. |
| 英文描述： | Wideband, High Output Current,Fast Settling Op Amp(寬帶,高輸出電流,快速運(yùn)算放大器) |
| 中文描述： | 寬帶，高輸出電流，快速沉降運(yùn)算放大器（寬帶，高輸出電流，快速運(yùn)算放大器） |
| 文件頁(yè)數(shù)： | 6/8頁(yè) |
| 文件大?。?/td> | 236K |
| 代理商： | AD842 |
AD842
REV. D
–6–
Figure 19b. Inverter Large Signal
Pulse Response
Figure 20b. Noninverting Large
Signal Pulse Response
Figure 19c. Inverter Small Signal
Pulse Response
Figure 20c. Noninverting Signal
Pulse Response
Figure 19a. Inverting Amplifier
Configuration (DIP Pinout)
Figure 20a. Noninverting Amplifier
Configuration (DIP Pinout)
OFFSE T NULLING
T he input offset voltage of the AD842 is very low for a high
speed op amp, but if additional nulling is required, the circuit
shown in Figure 21 can be used.
AD842 SE T T LING T IME
Figures 22 and 24 show the settling performance of the AD842
in the test circuit shown in Figure 23.
Settling time is defined as:
T he interval of time from the application of an ideal step
function input until the closed-loop amplifier output has
entered and remains within a specified error band.
T his definition encompasses the major components which com-
prise settling time. T hey include (1) propagation delay through
the amplifier; (2) slewing time to approach the final output
value; (3) the time of recovery from the overload associated with
slewing and (4) linear settling to within the specified error band.
Expressed in these terms, the measurement of settling time is
obviously a challenge and needs to be done accurately to assure
the user that the amplifier is worth consideration for the
application.
Figure 21. Offset Nulling (DIP Pinout)
Figure 22. AD842 0.01% Settling Time
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