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| 型號： | AD840JQ |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 運動控制電子 |
| 英文描述： | Wideband, Fast Settling Op Amp |
| 中文描述： | OP-AMP, 1500 uV OFFSET-MAX, 400 MHz BAND WIDTH, CDIP14 |
| 封裝： | HERMETIC SEALED, CERDIP-14 |
| 文件頁數(shù)： | 3/20頁 |
| 文件大?。?/td> | 463K |
| 代理商： | AD840JQ |
REV. C
–3–
AD8400/AD8402/AD8403
SPECIFICATIONS
(V
DD
= 3 V 10% or 5 V 10%, V
A
= V
DD
, V
B
= 0 V, –40 C
≤
T
A
≤
+125 C unless otherwise noted.)
ELECTRICAL CHARACTERISTICS–50 k and 100 k
VERSIONS
Parameter
Symbol
Conditions
Min
Typ
1
Max
Unit
DC CHARACTERISTICS RHEOSTAT MODE (Specifications Apply to All VRs)
Resistor Differential NL
Resistor Nonlinearity
2
Nominal Resistance
3
R-DNL
R-INL
R
AB
R
AB
R
AB
/
T
R
W
R/R
AB
R
WB
, V
A
= No Connect
R
WB
, V
A
= No Connect
T
A
= 25
°
C, Model: AD840XYY50
T
A
= 25
°
C, Model: AD840XYY100
V
AB
= V
, Wiper = No Connect
I
W
= 1 V/R
CH 1 to 2, 3, or 4,
V
AB
= V
DD
, T
A
= 25
°
C
–
1
–
2
35
70
±
1/4
±
1/2
50
100
500
53
0.2
+1
+2
65
130
LSB
LSB
k
k
ppm/
°
C
%
Resistance Tempco
Wiper Resistance
Nominal Resistance Match
100
1
DC CHARACTERISTICS POTENTIOMETER DIVIDER (Specifications Apply to All VRs)
Resolution
Integral Nonlinearity
4
Differential Nonlinearity
4
N
INL
DNL
DNL
DNL
V
W
/
T
V
WFSE
V
WZSE
8
–
4
–
1
–
1
–
1.5
Bits
LSB
LSB
LSB
LSB
ppm/
°
C
LSB
LSB
±
1
±
1/4
±
1/4
±
1/2
15
–
0.25
+0.1
+4
+1
+1
+1.5
V
DD
= 5 V
V
DD
= 3 V T
A
= 25
°
C
V
DD
= 3 V T
A
=
–
40
°
C, +85
°
C
Code = 80
H
Code = FF
H
Code = 00
H
Voltage Divider Tempco
Full-Scale Error
Zero-Scale Error
–
1
0
0
+1
RESISTOR TERMINALS
Voltage Range
Capacitance
Ax, Bx
Capacitance
6
Wx
Shutdown Current
7
Shutdown Wiper Resistance
V
A, B, W
C
A, B
C
W
I
A_SD
R
W_SD
0
V
DD
V
pF
pF
μ
A
f = 1 MHz, Measured to GND, Code = 80
H
f = 1 MHz, Measured to GND, Code = 80
H
V
A
= V
DD
, V
B
= 0 V,
SHDN
= 0
V
A
= V
DD
, V
B
= 0 V,
SHDN
= 0, V
DD
= 5 V
15
80
0.01
100
5
200
DIGITAL INPUTS AND OUTPUTS
Input Logic High
Input Logic Low
Input Logic High
Input Logic Low
Output Logic High
Output Logic Low
Input Current
Input Capacitance
6
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
I
IL
C
IL
V
DD
= 5 V
V
DD
= 5 V
V
DD
= 3 V
V
DD
= 3 V
R
L
= 2.2 k
to V
DD
I
OL
= 1.6 mA, V
= 5 V
V
IN
= 0 V or 5 V, V
DD
= 5 V
2.4
V
V
V
V
V
V
μ
A
pF
0.8
2.1
0.6
V
DD
–
0.1
0.4
±
1
5
POWER SUPPLIES
Power Supply Range
Supply Current (CMOS)
Supply Current (TTL)
Power Dissipation (CMOS)
9
Power Supply Sensitivity
V
DD
Range
I
DD
I
DD
P
PSS
PSS
2.7
5.5
5
4
27.5
0.001
0.03
V
μ
A
mA
μ
W
%/%
%/%
V
IH
= V
or V
= 0 V
V
IH
= 2.4 V or 0.8 V, V
DD
= 5.5 V
V
IH
= V
or V
= 0 V, V
DD
= 5.5 V
V
DD
= 5 V
±
10%
V
DD
= 3 V
±
10%
0.01
0.9
0.0002
0.006
DYNAMIC CHARACTERISTICS
6, 10
Bandwidth
–
3 dB
BW_50K
BW_100K
THD
W
t
S
_50K
t
S
_100K
e
NWB
_50K
e
NWB
_100K
C
T
R = 50 k
R = 100 k
V
A
= 1 V rms + 2 V dc, V
B
= 2 V dc, f = 1 kHz
V
A
= V
DD
, V
B
= 0 V,
±
1% Error Band
V
A
= V
, V
B
= 0 V,
±
1% Error Band
R
WB
= 25 k
, f = 1 kHz,
RS
= 0
R
WB
= 50 k
, f = 1 kHz,
RS
= 0
V
A
= V
DD
, V
B
= 0 V
125
71
0.003
9
18
20
29
–
65
kHz
kHz
%
μ
s
μ
s
nV/
√
Hz
nV/
√
Hz
dB
Total Harmonic Distortion
V
W
Settling Time
Resistor Noise Voltage
Crosstalk
11
NOTES
1
Typicals represent average readings at 25
°
C and V
= 5 V.
1
2
Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
1
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. See TPC 29 test circuit.
1
I
W
= V
DD
/R for V
= 3 V or 5 V for the 50 k
and 100 k
versions.
1
3
V
= V
, Wiper (V
) = No Connect.
1
4
INL and DNL are measured at V
with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. V
A
= V
DD
and V
B
= 0 V.
1
DNL Specification limits of
±
1 LSB maximum are Guaranteed Monotonic operating conditions. See TPC 28 test circuit.
1
5
Resistor terminals A, B, W have no limitations on polarity with respect to each other.
1
6
Guaranteed by design and not subject to production test. Resistor-terminal capacitance tests are measured with 2.5 V bias on the measured terminal. The remaining
1
resistor terminals are left open circuit.
1
7
Measured at the Ax terminals. All Ax terminals are open circuited in shutdown mode.
1
8
Worst-case supply current consumed when input logic level at 2.4 V, standard characteristic of CMOS logic. See TPC 20 for a plot of I
DD
versus logic voltage.
1
9
P
is calculated from (I
×
V
DD
). CMOS logic level inputs result in minimum power dissipation.
10
All Dynamic Characteristics use V
= 5 V.
11
Measured at a V
W
pin where an adjacent V
W
pin is making a full-scale voltage change.
Specifications subject to change without notice.
相關PDF資料 |
PDF描述 |
|---|---|
| AD840KN | Wideband, Fast Settling Op Amp |
| AD840KQ | Wideband, Fast Settling Op Amp |
| AD842* | Wideband. High Output Current. Fast Settling Op Amp |
| AD842SE | Voltage-Feedback Operational Amplifier |
| AD842JH | Wideband, High Output Current, Fast Settling Op Amp |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AD840KN | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Analog Devices 功能描述: |
| AD840KQ | 制造商:AD 制造商全稱:Analog Devices 功能描述:Wideband, Fast Settling Op Amp |
| AD840S | 制造商: 功能描述: 制造商:undefined 功能描述: |
| AD840SE/883B | 制造商:Rochester Electronics LLC 功能描述:PRECISION HIGH SPEED AMP - Bulk |
| AD840SE-883B | 制造商:AD 制造商全稱:Analog Devices 功能描述:Wideband, Fast Settling Op Amp |
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