參數(shù)資料
型號： AD8403AR1-REEL
廠商： Analog Devices Inc
文件頁數(shù)： 13/32頁
文件大?。?/td> 0K
描述： IC POT DIG QUAD 1K 8BIT 24SOIC
產(chǎn)品變化通告： Product Discontinuance 27/Oct/2011
標(biāo)準(zhǔn)包裝： 1,000
接片： 256
電阻（歐姆）： 1k
電路數(shù)： 4
溫度系數(shù)： 標(biāo)準(zhǔn)值 500 ppm/°C
存儲器類型： 易失
接口： 4 線 SPI（芯片選擇）
電源電壓： 2.7 V ~ 5.5 V
工作溫度： -40°C ~ 125°C
安裝類型： 表面貼裝
封裝/外殼： 24-SOIC（0.295"，7.50mm 寬）
供應(yīng)商設(shè)備封裝： 24-SOIC W
包裝： 帶卷 (TR)
AD8400/AD8402/AD8403
Rev. E | Page 20 of 32
THEORY OF OPERATION
The AD8400/AD8402/AD8403 provide a single, dual, and quad
channel, 256-position, digitally controlled variable resistor (VR)
device. Changing the programmed VR setting is accomplished
by clocking in a 10-bit serial data-word into the SDI (Serial
Data Input) pin. The format of this data-word is two address
bits, MSB first, followed by eight data bits, also MSB first.
Table 6 provides the serial register data-word format. The
AD8400/AD8402/AD8403 have the following address assign-
ments for the ADDR decoder, which determines the location
of the VR latch receiving the serial register data in Bit B7 to
Bit B0:
VR# = A1 × 2 + A0 + 1
(1)
The single-channel AD8400 requires A1 = A0 = 0. The dual-
channel AD8402 requires A1 = 0. VR settings can be changed
one at a time in random sequence. A serial clock running at
10 MHz makes it possible to load all four VRs under 4 μs
(10 × 4 × 100 ns) for AD8403. The exact timing requirements
are shown in Figure 3, Figure 4, and Figure 5.
The AD8400/AD8402/AD8403 do not have power-on midscale
preset, so the wiper can be at any random position at power-up.
However, the AD8402/AD8403 can be reset to midscale by
asserting the RS pin, simplifying initial conditions at power-up.
Both parts have a power shutdown SHDN pin that places the
VR in a zero-power-consumption state where Terminal Ax is
open-circuited and the Wiper Wx is connected to Terminal Bx,
resulting in the consumption of only the leakage current in the
VR. In shutdown mode, the VR latch settings are maintained
so that upon returning to the operational mode, the VR settings
return to the previous resistance values. The digital interface is
still active in shutdown, except that SDO is deactivated. Code
changes in the registers can be made during shutdown that will
produce new wiper positions when the device is taken out of
shutdown.
D7
D6
D5
D4
D3
D2
D1
D0
RDAC
LATCH
AND
DECODER
Ax
Wx
Bx
RS =RNOMINAL/256
RS
SHDN
RS
01
09
2-
0
44
Figure 45. AD8402/AD8403 Equivalent VR (RDAC) Circuit
PROGRAMMING THE VARIABLE RESISTOR
Rheostat Operation
The nominal resistance of the VR (RDAC) between Terminal A
and Terminal B is available with values of 1 kΩ, 10 kΩ, 50 kΩ,
and 100 kΩ. The final digits of the part number determine the
nominal resistance value; that is, 10 kΩ = 10; 100 kΩ = 100.
The nominal resistance (RAB) of the VR has 256 contact points
accessible by the wiper terminal, and the resulting resistance
can be measured either across the wiper and B terminals (RWB)
or across the wiper and A terminals (RWA). The 8-bit data-word
loaded into the RDAC latch is decoded to select one of the
256 possible settings. The wiper’s first connection starts at the
B terminal for data 00H. This B terminal connection has a wiper
contact resistance of 50 Ω. The second connection (for the 10 kΩ
part) is the first tap point located at 89 Ω = [RAB (nominal
resistance) + RW = 39 Ω + 50 Ω] for data 01H. The third
connection is the next tap point representing 78 Ω + 50 Ω =
128 Ω for data 02H. Each LSB data value increase moves the
wiper up the resistor ladder until the last tap point is reached at
10,011 Ω. Note that the wiper does not directly connect to the
B terminal even for data 00H. See Figure 45 for a simplified
diagram of the equivalent RDAC circuit.
The AD8400 contains one RDAC, the AD8402 contains
two independent RDACs, and the AD8403 contains four
independent RDACs. The general transfer equation that
determines the digitally programmed output resistance
between Wx and Bx is
()
W
AB
WB
R
D
R
+
×
=
256
(2)
where D, in decimal, is the data loaded into the 8-bit RDAC#
latch, and RAB is the nominal end-to-end resistance.
For example, when the A terminal is either open-circuited or
tied to the Wiper W, the following RDAC latch codes result in
the following RWB (for the 10 kΩ version):
Table 10.
D (Dec)
RWB (
)
Output State
255
10,011
Full scale
128
5,050
Midscale (RS = 0 condition)
1
89
1 LSB
0
50
Zero-scale (wiper contact resistance)
Note that in the zero-scale condition, a finite wiper resistance of
50 Ω is present. Care should be taken to limit the current flow
between W and B in this state to a maximum value of 5 mA to
avoid degradation or possible destruction of the internal switch
contact.
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