參數(shù)資料
型號(hào)： AD8330ARQ
廠商： ANALOG DEVICES INC
元件分類(lèi)： 消費(fèi)家電
英文描述： Low Cost DC-150 MHz Variable Gain Amplifier
中文描述： SPECIALTY CONSUMER CIRCUIT, PDSO16
封裝： MO-137AB, QSOP-16
文件頁(yè)數(shù)： 20/28頁(yè)
文件大?。?/td> 681K
代理商： AD8330ARQ
REV. A
–20–
AD8330
FREQUENCY – Hz
90
50k
C
–10
10
30
50
70
100k
1M
100M
80
0
20
40
60
10M
OFST: ENABLED
DISABLED
V
DBS
= 1.5V
V
DBS
= .75V
V
DBS
= 0V
Figure 16. Input CMRR vs. Frequency for Various
Values of V
DBS
Using Single-Sided Sources and Loads
Where the source provides a single-sided output, either INHI or
INLO may be used for the input, with of course a polarity change
when using INLO. The unused pin must be connected either
through a capacitor to ground, or a dc bias point that corresponds
closely to the dc level on the active signal pin. The input CMRR
over the full frequency range is illustrated in Figure 16. In some
cases, an additional element such as a SAW filter (having a single-
sided-balanced configuration) or a flux-coupled transformer may
be interposed. Where this element must be terminated in the
correct impedance, other than 1 k
, it will be necessary to add
either shunt or series resistors at this interface.
FREQUENCY – Hz
30
1M
–600
P
G
–20
–30
–10
0
10
20
–400
–300
–200
–100
0
LINE 1
LINE 3
LINE 4
LINE 2
LINE 4
LINE 1
LINE 3
LINE 2
10M
100M
500M
–500
Figure 17. AC Gain and Phase for Various Loading Conditions
When driving a single-sided load, either OPHI or OPLO may be
used. These outputs are very symmetric, so the only effect of
this choice is to select the desired polarity. However, when the
frequency range of interest extends to the upper limits of the
AD8330, a dummy resistor of the same value should be attached
to the unused output. Figure 17 illustrates the ac gain and phase
response for various loads and V
DBS
= 0.75 V. Line 1 shows the
unloaded (C
L
= 12 pF) case for reference; the gain is 6 dB lower
(20 dB) using just the single-sided output. Adding a 75
load
just from OPHI to an ac ground results in Line 2. The gain is
now a factor of 1.5 or 3.54 dB lower, but artifacts of the output
common-mode control loop now appear in both the magnitude
and phase response.
Adding a dummy 75
to OPLO results in Line 3: the gain is a
further 2.5 dB lower, at about 14 dB. The CM artifacts are no
longer present but there is now a small amount of peaking. If
objectionable, this may be eliminated by raising both of the
capacitors on the output pins to 25 pF, as shown in Line 4.
The gain reduction incurred both by using only one output and
by the additional effect of loading can be overcome by taking
advantage of the V
MAG
feature, provided primarily for just such
circumstances. Thus, to restore the basic gain in the first case
(Line 1), a 1 V source should be applied to this pin; to restore
the gain in the second case, this voltage should be raised by a
factor of 1.5, to 1.5 V. In cases 3 and 4, a further factor of
1.33 is needed to make up the 2.5 dB loss, that is, V
MAG
should
be raised to 2 V. With the restoration of gain, the peak output
swing at the load is likewise restored to
±
2 V.
Pulse Operation
When using the AD8330 in applications where its transient response
is of greater interest and the outputs are conveyed to their load via
coaxial cables, the added capacitances may be slightly different in
value, and may be placed either at the sending or load end of the
cables, or divided between these nodes. Figure 18 shows an illustra-
tive example in which dual 1 meter 75
cables are driven through
dc-blocking capacitors and independently terminated at ground level.
Because of the considerable variation between applications, only
general recommendations can be made with regard to minimizing
pulse overshoot and droop. The former can be optimized by adding
small load capacitances, if necessary; the latter require the use
of sufficiently large capacitors C1.
COMM
OPHI
INLO
OPLO
INHI
VPSI
VPSO
CMOP
MODE
VDBS
CMGN
VMAG
OFST
ENBL
CNTR
VPOS
BIAS AND
V-REF
GAIN INTERFACE
CM MODE AND
OFFSET CONTROL
OUTPUT
STAGES
OUTPUT
CONTROL
VGA CORE
NC
CD2
CD3
RD2
V
S
2.7V–6V
C1
C1
CL1
CL2
RL1
RL2
Figure 18. Driving Dual Cables with Grounded Loads
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