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參數(shù)資料
| 型號： | AD8330ARQ |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費家電 |
| 英文描述： | Low Cost DC-150 MHz Variable Gain Amplifier |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PDSO16 |
| 封裝： | MO-137AB, QSOP-16 |
| 文件頁數(shù)： | 18/28頁 |
| 文件大?。?/td> | 681K |
| 代理商： | AD8330ARQ |
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REV. A
–18–
AD8330
Offset Compensation
The AD8330 includes an offset compensation feature, which is
operational in the default condition (no connection to pin OFST).
This loop introduces a high-pass filter function into the signal
path, whose
–
3 dB corner frequency is at:
f
HPF
=
(
)
1
2
π
R
C
INT
HP
(11)
where
C
HP
is the external capacitance added from OFST to CNTR,
and
R
INT
is an internal resistance of approximately 480
, having a
maximum uncertainty of about
±
20%. This evaluates to:
μ
μ
(
C
HP
A small amount of peaking at this corner when using small capacitor
values can be avoided by adding a series resistor. Useful combina-
tions are C
HP
= 3 nF, R
HP
= 180
, f = 100 kHz; C
HP
= 33 nF,
R
HP
= 10
, f = 10 kHz; C
HP
= 0.33
μ
F, R
HP
= 0
, f = 1 kHz;
C
HP
= 3.3
μ
F, R
HP
= 0
, f = 100 Hz.
The offset compensation feature can be disabled simply by ground-
ing the OFST pin. This provides a dc-coupled signal path, with
no other effects on the overall ac response. Input offsets must be
externally nulled in this mode of operation, as shown in Figure 15.
Effects of Loading on Gain and AC Response
The differential output impedance R
O
is 150
and the frequency
response of the output stage is optimized for operation with a certain
load capacitance on each output pin, OPHI and OPLO, to
ground, in combination with a load resistance R
L
directly across
these pins. In the absence of these capacitances, there will be a
small amount of peaking at the top extremity of the ac response.
Suitable combinations are: R
L
=
∞
, C
L
= 12 pF; R
L
= 150
,
C
L
= 25 pF; R
L
= 75
, C
L
= 40 pF; R
L
= 50
, C
L
= 50 pF.
The gain calibration is specified for an open-circuited load, such
as the high input resistance of an ADC. When resistively loaded,
all gain values are nominally lowered as follows:
f
HPF
≈
)
330
C
in
F
HP
(12)
G
G
LOADED
UNLOADED
(
=
+
)
R
R
L
L
150
(13)
Thus when
R
L
= 150
, the gain is reduced by 6 dB; for R
L
= 75
,
the reduction is 9.5 dB; and for R
L
= 50
, it is 12 dB.
Gain Errors Due to On-Chip Resistor Tolerances
In all cases where external resistors are used, keep in mind that all
on-chip resistances, including the R
O
and the input resistance,
R
I
, are subject to variances of up to
±
20%, which will need to
be accounted for when calculating the gain with input and output
loading. This sensitivity can be avoided by adjusting the source
and load resistances to bear an inverse relationship as follows:
If R
S
=
α
R
I
then make R
L
= R
O
/
α
; or, if R
L
=
α
R
O
then make
R
S
= R
I
/
α
. The simplest case is when R
S
= 1 k
and R
L
= 150
.
Here the gain is 12 dB lower than the basic value. The reduction
of peak swing at the load can be corrected by using V
MAG
= 1 V,
which also restores 6 dB of gain; using V
MAG
= 2 V restores the
full basic gain while also doubling the peak available output swing.
Output (Input) Common-Mode Control
The output voltages are nominally positioned at the midpoint of
the supply, V
S
/2, over the range 2.7 V < V
S
< 6 V, and this voltage
appears at pin CNTR, which is not normally expected to be
loaded (the source resistance is ~4 k
). However, some circum-
stances may require a small change in this voltage, and a resistor
from CNTR to ground can lower this voltage, or one to the supply
will raise it. On the other hand, this pin may be driven by an
external voltage source to set the common-mode level, to satisfy
the needs of a following ADC, for example. Any value from 0.5 V
above ground to 0.5 V below the supply is permissible. Of
course, when using an extreme common-mode level, the avail-
able output swing will be limited, and it is recommended that a
value equal or close to the default of V
CNTR
= V
S
/2 be used. There
may be a few millivolts of offset between the applied voltage and the
actual common-mode level at the output pins.
The input common-mode voltage V
CMI
at pins INHI, INLO is
slaved to the output, but with a shifted value:
V
CMI
=
+
0 757
.
1 12
.
V
V
CNTR
(14)
for V
DBS
= 0.75 and T = 25
°
C. Thus, the default value for V
CMI
when V
S
= 5 V is 3.01 V (see Figure 12).
USING THE AD8330
There are very few precautions that need to be observed in apply-
ing the AD8330 to a wide variety of circumstances. A selection
of specific applications is presented later. Here we discuss a few
general aspects of utilization.
As in all high frequency circuits, careful observation of the ground
nodes associated with each function is important. Three positive
supply pins are provided. VPSI supports the input circuitry, which
may often be operating at a relatively high sensitivity; VPOS,
which supports general bias sources, needs no decoupling; VPSO
is used to bias the output stage, where decoupling may be useful
in maintaining a glitch-free output. Figure 14 shows the general
case, where VPSI and VPSO are each provided with their own
decoupling network, but this may not be needed in all cases.
Because of the differential nature of the signal path, power-supply
decoupling is in general much less critical than in a single-sided
amplifier, and where the minimization of board-level components
is especially crucial, it may be found that these pins need no
decoupling at all. On the other hand, when the signal source is
COMM
OPHI
INLO
OPLO
INHI
VPSI
VPSO
CMOP
MODE
VDBS
CMGN
VMAG
OFST
ENBL
CNTR
VPOS
BIAS AND
V-REF
GAIN INTERFACE
CM MODE AND
OFFSET CONTROL
OUTPUT
STAGES
OUTPUT
CONTROL
VGA CORE
OUTPUT,
2V MAX
NC
BASIC GAIN BIAS
V
DBS:
0V TO 1.5V
RD1
CHPF
CD2
CD1
CD3
RD2
GROUND
V
S
2.7V–6V
INPUT,
0V TO 2V MAX
NC
Figure 14. Power Supply Decoupling and Basic Connections
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