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參數(shù)資料
| 型號： | AD8330ARQ-REEL7 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費家電 |
| 英文描述： | Low Cost DC-150 MHz Variable Gain Amplifier |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PDSO16 |
| 封裝： | MO-137AB, QSOP-16 |
| 文件頁數(shù)： | 23/28頁 |
| 文件大?。?/td> | 681K |
| 代理商： | AD8330ARQ-REEL7 |
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REV. A
AD8330
–23–
Figure 20 shows the connections. A 3.3 V supply is used for
both parts. The ADC requires that its input pins be positioned
at one third of the supply, or 1.1 V. Since the default output
level of the VGA is one half the supply or 1.65 V, a small correc-
tion is introduced by the 8 k
resistor from CNTR to ground.
The ADC specifications require that the common-mode input
be within
±
0.2 V of the nominal 1.1 V; variations of up to
±
20%
in the AD8330
’
s on-chip resistors will change this voltage by
only
±
70 mV. With the connections shown, the AD9214 is able
to receive an input of 2 V p-p; the peak output of the AD8330
can be reduced if desired by adding a resistor from VMAG to
ground. An overrange condition is signaled by a HI state on pin
OR of the AD9214. DFS/GAIN is unconnected in this example;
this produces an offset-binary output. To provide a twos comple-
ment output, it should be connected to the REF pin.
For ADCs running at sampling rates substantially below the
bandwidth of the AD8330, an intervening noise filter is recom-
mended to limit the noise bandwidth. A one-pole filter can
easily be created with a single differential capacitor between
OPHI and OPLO outputs. For a corner frequency of
fc
, the
capacitor should have a value of
=
1 942
/
C
f
FILT
C
(26)
For example a 10 MHz corner requires about 100 pF.
Simple AGC Amplifier
Figure 21 illustrates the use of the inverted gain mode and the
offset gain range (0.2 V < V
DBS
< 1.7 V) in supporting a low cost
AGC loop. Q1 is used as a detector: when OPHI is sufficiently
higher than CNTR, due to the signal swing it conducts and
charges C1; this raises V
DBS
and rapidly lowers the gain. Note
that MODE is grounded (see Figure 5). The minimum voltage
needed across R1 to set up the full gain is now 0.2 V, since
CMGN is dc open-circuited (this does not alter V
MAG
), while the
maximum is 1.7 V.
COMM
OPHI
INLO
OPLO
INHI
VPSI
VPSO
CMOP
MODE
VDBS
CMGN
VMAG
OFST
ENBL
CNTR
VPOS
BIAS AND
V-REF
CM MODE AND
OFFSET CONTROL
OUTPUT
OUTPUT
VGA CORE
NC
5mVINPUT,
0.1 F
10
GAIN INTERFACE
33nF
R1
100k
0.1 F
0.1 F
4.7
Q2
Q1
SEE
TEXT
C1
0.1 F
V
S
, 2.7V–6V
0.1 F
OUTPUT,
~1V rms
Figure 21. Simple AGC Amplifier (Preliminary)
When the loop is settled, the average current in Q1 is V
DBS
/R1,
which varies from 2
μ
A at maximum gain (V
DBS
= 0.2 V) to 17
μ
A at minimum gain (V
DBS
= 1.7 V). This change in Q1
’
s cur-
rent causes an increase of ~0.25 dB over the full gain range in
the differential output of nominally 0.75 dBV at midrange (3.08
V p-p), corresponding to a 200:1 compression ratio. This is
plotted in Figure 22 for a representative 100 kHz input.
COMM
OPHI
INLO
OPLO
INHI
VPSI
VPSO
CMOP
MODE
VDBS
CMGN
VMAG
OFST
ENBL
CNTR
VPOS
BIAS AND
V-REF
CM MODE AND
OFFSET CONTROL
OUTPUT
OUTPUT
CONTROL
VGA CORE
AD9217BRS-80
D
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DGND
CLK
AGND
CLOCK
REF
0.1 F
REFSENSE
NC
ANALOG GROUND
A
IN
A
IN
DFS/GAIN
PWRDN
DIGITAL
GROUND
GAIN BIAS,
V
DBS
, 0V–1.5V
NC
INPUT,
2V MAX
0.1 F
10
GAIN INTERFACE
CHPF
8k
0.1 F
0.1 F
AV
DD
OR
DrV
DD
3.3
OVER-
RANGE
3.3
0.1 F
V
S
, 3.3V
Figure 20. Driving an Analog-to-Digital Converter (Preliminary)
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