參數(shù)資料
型號(hào)： AD8330ARQ-REEL7
廠(chǎng)商： ANALOG DEVICES INC
元件分類(lèi)： 消費(fèi)家電
英文描述： Low Cost DC-150 MHz Variable Gain Amplifier
中文描述： SPECIALTY CONSUMER CIRCUIT, PDSO16
封裝： MO-137AB, QSOP-16
文件頁(yè)數(shù)： 14/28頁(yè)
文件大小： 681K
代理商： AD8330ARQ-REEL7
REV. A
–14–
AD8330
The pin-to-pin input resistance is specified as 950
±
20%.
The driving-point impedance of the signal source may range
from zero up to values considerably in excess of this resis-
tance, with a corresponding variation in noise figure (see
Figure 10). In most cases, the input will be coupled via two
capacitors, chosen to provide adequate low frequency trans-
mission. This results in the minimum input noise, which is
increased when some other common-mode voltage is forced
onto these pins, as explained later. The short circuit, input-
referred noise at maximum gain is approximately 5 nV/
√
Hz
.
The output pins OPHI/OPLO operate at a common-mode
voltage at the midpoint of the supply, V
S
/2, within a few millivolts.
This ensures that an analog-to-digital converter (ADC) attached
to these outputs operates within the often narrow range permit-
ted by their design. When a common-mode voltage other than V
S
/2
is required at this interface, it can easily be forced by applying an
externally provided voltage to the output centering pin, CNTR.
This voltage may run from zero to the full supply, though it
must be noted that the use of such extreme values would
leave only a small range for the differential output signal swing.
The differential impedance measured between OPHI and
OPLO is 150
±
20%. It follows that both the gain and the
full-scale voltage swing will depend on the load impedance;
both are nominally halved when this is also 150
. A fixed-
impedance output interface, rather than an op amp style
voltage-mode output, is preferable in high speed applications
since the effects of complex reactive loads on the gain and
phase can be better controlled. The top end of the AD8330
’
s
ac response is optimally flat for a 12 pF load on each pin, but
this is not critical and the system will remain stable for any
value of load capacitance including zero.
Another useful feature of this VGA in connection with the driving
of an ADC is that the peak output magnitude can be precisely
controlled by the voltage on pin V
MAG
. Usually, this voltage is
internally preset to 500 mV, and the peak differential, unloaded
output swing is
±
2 V
±
3%. However, any voltage from zero to
at least 5 V can be applied to this pin to alter the peak output in
an exactly proportional way. Since either output pin can swing
“
rail to rail,
”
which in practice means down to at least 0.35 V
and to within the same voltage below the supply, the peak-to-peak
output between these pins can be as high as 10 V using V
S
= 6 V.
INHI
INLO
VDBS
VPSI
COMM
TRANSIMPEDANCE
OUTPUT STAGE
500
500
LINEAR-IN-dB
INTERFACE
MAGNITUDE
INTERFACE
5k
R
OUT =
150
100 A
V
MAG
VPSO
OPHI
OPLO
V = 0
12.65 A–4mA OR
4mA–12.65 A
COMM
VMAG
MODE
CNTR
V = 0
O/P CM-MODE
NORMALLY
AT V
P
/2
CM MODE
FEEDBACK
V
DBS
Figure 4. Schematic of Key Components
Linear-in-dB Gain Control (V
DBS
)
A gain control law that is linear in decibels is frequently claimed
for VGAs based more loosely on these principles. However, closer
inspection reveals that their conformance to this ideal gain func-
tion is poor, usually only an approximation over part of the gain
range. Furthermore, the calibration (so many decibels per volt)
is invariably left unspecified, and the resulting gain often varies
wildly with temperature. All Analog Devices VGAs featuring a
linear-in-dB gain law, such as the X-AMP
family, provide exact,
constant gain scaling over the fully specified gain range, and the
deviation from the ideal response is within a small fraction of a dB.
For the AD8330, the scaling of both its gain interfaces is substan-
tially independent of process, supply voltage, or temperature.
The Basic Gain,
G
B
, is simply:
V
B
dB
mV
where V
DBS
is in volts. Alternatively, this can be expressed as a
numerical gain magnitude:
V
DBS
=
10
0 6
V
As discussed later, the gain may be increased or decreased by
changing the voltage V
MAG
applied to the VMAG pin. The internally
set default value of 500 mV is derived from the same band gap
reference that determines the decibel scaling. The tolerance on this
voltage, and mismatches in certain on-chip resistors, cause small
gain errors (see Specifications). While not all applications of VGAs
demand accurate gain calibration, there are many situations in which
it will be a valuable asset, for example, in reducing design tolerances.
Figure 4 shows the core circuit in somewhat more detail. The
range and scaling of V
DBS
is independent of the supply voltage,
and the gain-control pin, VDBS, presents a high incremental input
resistance (~100 M
) with a low bias current (~100 nA), making
the AD8330 easy to drive from a variety of gain-control sources.
Inversion of the Gain Slope
The AD8330 supports many new features that further extend
the versatility of this VGA in wide bandwidth, gain-control sys-
tems. For example, the logic pin MODE allows the slope of the
gain function to be inverted, so that the basic gain starts at +50 dB
for a gain voltage V
DBS
of zero and runs down to 0 dB when this
voltage is at its maximum specified value of 1.5 V. The basic
forms of these two gain control modes are shown in Figure 5.
G
DBS
(
)
=
30
(1)
G
BN
(2)
0.25
10
20
V
d
0
30
40
50
0
0.50
0.75
1.0
1.25
1.50
MODE PIN
LOW, GAIN
DECREASES
WITH V
DBS
MODE PIN
HIGH, GAIN
INCREASES
WITH V
DBS
Figure 5. The Two Gain Directions of the AD8330
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