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參數(shù)資料
| 型號(hào)： | AD8320 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Serial Digital Controlled Variable Gain Amplifier(串行數(shù)字驅(qū)動(dòng)可變?cè)鲆娣糯笃? |
| 中文描述： | 串行數(shù)字控制可變?cè)鲆娣糯笃鳎ù袛?shù)字驅(qū)動(dòng)可變?cè)鲆娣糯笃鳎?/td> |
| 文件頁數(shù)： | 3/20頁 |
| 文件大?。?/td> | 513K |
| 代理商： | AD8320 |
AD8320
–3–
REV. 0
LOGIC INPUTS (TTL/CMOS Logic)
Parameter
Min
T yp
Max
Units
Logic “1” Voltage
Logic “0” Voltage
Logic “1” Current (V
INH
= 5 V) CLK , SDAT A,
DATEN
Logic “0” Current (V
INL
= 0 V) CLK , SDAT A,
DATEN
Logic “1” Current (V
INH
= 5 V)
PD
Logic “0” Current (V
INL
= 0 V)
PD
TIMNGREQUIREMENTS
2.1
0
0
–450
0
–320
5.0
0.8
20
–75
190
–70
V
V
nA
nA
μ
A
μ
A
Parameter
Min
T yp
Max
Units
Clock Pulse Width (T
WH
)
Clock Period (T
C
)
Setup T ime SDAT A vs. Clock (T
DS
)
Setup T ime
DATEN
vs. Clock (T
ES
)
Hold T ime SDAT A vs. Clock (T
DH
)
Hold T ime
DATEN
vs. Clock (T
EH
)
Input Rise and Fall T imes, SDAT A,
DATEN
, Clock (T
R
, T
F
)
12.0
32.0
6.5
17.0
5.0
3.0
ns
ns
ns
ns
ns
ns
ns
10
T
ES
VALIMSB. . . .LSB
GAIN TRANSFER (G1)
T
DS
T
EH
8 CLOCK CYCLES
GAIN TRANSFER (G2)
T
OFF
T
GS
ANALOG
OUTPUT
SIGNAL AMPLITUDE (p-p)
PD
PEDESTAL
CLK
SDATA
DATEN
T
ON
T
C
T
WH
VALID DATA WORD G2
Figure 2. Serial Interface Timing
VALID DATA BIT
MSB
MSB-1
MSB-2
T
DS
T
DH
CLK
Figure 3.
(
DATEN
, CLK, SDATA, 5 V
≤
V
CC
≤
12 V; Full Temperature Range)
(Full Temperature Range, V
CC
Supply Range, T
R
= T
F
= 4 ns, F
CLK
= 8 MHz unless otherwse noted.)
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD8320ARP | 制造商:Analog Devices 功能描述:SP Amp Line Driver Amp Single 12V 20-Pin PSOP-II Tube 制造商:Rochester Electronics LLC 功能描述:PSOP 8-BIT SER, 200MHZ DIGITAL CTRL VGA - Bulk |
| AD8320ARP-REEL | 制造商:Analog Devices 功能描述:SP Amp Line Driver Amp Single 12V 20-Pin PSOP-II T/R |
| AD8320ARPZ | 制造商:Analog Devices 功能描述:SP Amp Line Driver Amp Single 12V 20-Pin PSOP-II Tube |
| AD8320-EB | 制造商:Analog Devices 功能描述: |
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