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參數(shù)資料
| 型號： | AD831 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Low Distortion Mixer |
| 中文描述： | 低失真混頻器 |
| 文件頁數(shù)： | 8/16頁 |
| 文件大?。?/td> | 225K |
| 代理商： | AD831 |
AD831
REV. B
–8–
Low-Pass Filtering
A simple low-pass filter may be added between the mixer and
the output amplifier by shunting the internal resistive loads (an
equivalent resistance of about 14
with a tolerance of 20%)
with external capacitors; these attenuate the sum component in
a down-conversion application (Figure
20). T he corner fre-
quency of this one-pole low-pass filter (f = (2
π
RC
F
)
–1
) should
be placed about an octave above the difference frequency IF.
T hus, for a 70 MHz IF, a –3 dB frequency of 140 MHz might
be chosen, using C
F
= (2
× π
×
14
×
140 MHz)
–1
≈
82 pF, the
nearest standard value.
IFN
VP
IFP
50
AP
GND
VN
RFP
RFN
VN
VP
9
LON
LOP
VP
12
GND
13
BIAS
VN
AD831
Top View
50
6
7
8
4
5
10
11
AN
VFB
COM
OUT
14
15
16
17
18
1
2
3
19
20
C
F
C
F
C
F
= 2
π
f R
1
1
89.7 f
Figure 20. Low-Pass Filtering Using External Capacitors
Using the Output Amplifier
T he AD831’s output amplifier converts the mixer core’s dif-
ferential current output into a single-ended voltage and provides
an output as high as
±
1 V peak into a 50
load (+10 dBm).
For unity gain operation (Figure 21), the inputs AN and AP
connect to the open-collector outputs of the mixer’s core and
OUT connects to VFB.
IF
OUTPUT
IFN
VP
IFP
50
AP
GND
VN
RFP
RFN
VN
VP
9
LON
LOP
VP
12
GND
13
BIAS
VN
AD831
Top View
50
6
7
8
4
5
10
11
AN
VFB
COM
OUT
14
15
16
17
18
1
2
3
19
20
Figure 21. Output Amplifier Connected for Unity Gain
Operation
T he mixer has two open-collector outputs (differential cur-
rents) at pins IFN and IFP. T hese currents may be used to pro-
vide nominal unity RF-to-IF gain by connecting a center-tapped
transformer (1:1 turns ratio) to pins IFN and IFP as shown in
Figure 18.
20
2
Q3
R5
1k
LIMITING
AMPLIFIER
VP
1
18mA TYP
IFN
IFP
18mA TYP
5k
5k
Q1
Q2
Q5
Q6
Q4
R4
1k
R1
20
R2
20
R3
26
Q7
36mA TYP
LOP
LON
RFP
RFN
VP
BIAS
VN
LOCAL
OSCILLATOR
INPUT
RF
INPUT
10
11
6
7
BIAS
CURRENT
IF OUTPUT
VPOS
MCLT4-1H
Figure 18. Connections for Transformer Coupling to the IF
Output
Programming the Bias Current
Because the AD831’s RF port is a Class-A circuit, the maxi-
mum RF input is proportional to the bias current. T his bias cur-
rent may be reduced by connecting a resistor from the BIAS pin
to the positive supply (Figure 19
)
. For normal operation, the
BIAS pin is left unconnected. For lowest power consumption,
the BIAS pin is connected directly to the positive supply. T he
range of adjustment is 100 mA for normal operation to
45 mA total current at minimum power consumption.
1.33k
0.1μF
VPOS
NOTE ADDED
RESISTOR
IFN
VP
IFP
50
AP
GND
VN
RFP
RFN
VN
VP
9
LON
LOP
VP
12
GND
13
BIAS
VN
AD831
Top View
50
6
7
8
4
5
10
11
AN
VFB
COM
OUT
14
15
16
17
18
1
2
3
19
20
Figure 19. Programming the Quiescent Current
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