參數資料
型號: AD8194ACPZ
廠商: Analog Devices Inc
文件頁數: 11/16頁
文件大?。?/td> 0K
描述: IC TMDS SWITCH BUFF 2:1 32LFCSP
標準包裝: 1
功能: 開關
電路: 4 x 2:1
電壓電源: 單電源
電壓 - 電源,單路/雙路(±): 3 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 32-VFQFN 裸露焊盤,CSP
供應商設備封裝: 32-LFCSP-VQ
包裝: 托盤
產品目錄頁面: 775 (CN2011-ZH PDF)
AD8194
Rev. 0 | Page 4 of 16
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
Rating
AVCC to AVEE
3.7 V
VTTI
AVCC + 0.6 V
VTTO
AVCC + 0.6 V
Internal Power Dissipation
1.2 W
High Speed Input Voltage
AVCC 1.4 V < VIN < AVCC + 0.6 V
High Speed Differential
Input Voltage
2.0 V
Source Select (S_SEL)
AVEE 0.3 V < VIN < AVCC + 0.6 V
Storage Temperature Range
65°C to +125°C
Operating Temperature
Range
40°C to +85°C
Junction Temperature
150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θ
JA
is specified for the worst-case conditions: a device soldered
in a 4-layer JEDEC circuit board for surface-mount packages.
θ
JC
is specified for the exposed pad soldered to the circuit board
with no airflow.
Table 3. Thermal Resistance
Package Type
θ
JA
θ
JC
Unit
32-Lead LFCSP
47
6.8
°C/W
MAXIMUM POWER DISSIPATION
The maximum power that can be safely dissipated by the
AD8194 is limited by the associated rise in junction tempera-
ture. The maximum safe junction temperature for plastic
encapsulated devices is determined by the glass transition
temperature of the plastic, approximately 150°C. Temporarily
exceeding this limit may cause a shift in parametric performance
due to a change in the stresses exerted on the die by the package.
Exceeding a junction temperature of 175°C for an extended
period can result in device failure. To ensure proper operation,
it is necessary to observe the maximum power derating as
determined by the coefficients in Table 3.
ESD CAUTION
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