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參數(shù)資料
| 型號： | AD8185ARU-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 2/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MULTIPLEXER TRPL 2X1 24TSSOP |
| 標準包裝： | 1,000 |
| 功能： | 多路復用器 |
| 電路： | 3 x 2:1 |
| 電壓電源： | 雙電源 |
| 電壓 - 電源，單路/雙路(±)： | ±4.5 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-TSSOP（0.173"，4.40mm 寬） |
| 供應商設備封裝： | 24-TSSOP |
| 包裝： | 帶卷 (TR) |
REV. 0
AD8183/AD8185
–10–
THEORY OF OPERATION
The AD8183 (G = +1) and AD8185 (G = +2) are triple-output,
2:1 multiplexers with TTL-compatible global input switching
and output enable control. Optimized for selecting between two
RGB (red, green, blue) video sources, the devices have high
peak slew rates, maintaining their bandwidth for large signals.
Additionally, the multiplexers are compensated for high phase
margin, minimizing overshoot for good pixel resolution. The
multiplexers also have video specifications that are suitable for
switching NTSC or PAL composite signals.
The multiplexers are organized as three independent channels,
each with two input transconductance stages and one output
transimpedance stage. The appropriate input transconductance
stages are selected via one logic pin (SELECT
A/B), such that
all three outputs switch input connections simultaneously. The
unused input stages are disabled with a “t-switch” scheme to
provide excellent crosstalk isolation between “on” and “off”
inputs. No additional input buffering is necessary, resulting in
low input capacitance and high input impedance without addi-
tional signal degradation.
The transconductance stages, NPN differential pairs, source
signal current into the folded cascode output stages. Each out-
put stage contains a compensating network and emitter follower
output buffer. Internal voltage feedback sets the gain with the
AD8183 being configured as a unity gain follower, and the
AD8185 as a gain-of-two amplifier with a feedback network.
This architecture provides drive for a reverse-terminated video
load (150
) with low differential gain and phase error for
relatively low power consumption. Careful chip design and
layout allow excellent crosstalk isolation between channels.
One logic pin
OE controls whether the three outputs are
enabled, or disabled to a high-impedance state. The high
impedance disable allows larger matrices to be built when
busing the outputs together. Also, when not in use the outputs
can be disabled to reduce power consumption. In the case of
the AD8185 (G = +2), a feedback isolation scheme is used so
that the impedance of the gain-of-two feedback network does
not load the output.
Note that full power bandwidth for an undistorted sinusoidal
signal is often calculated using peak slew rate from the equation:
Full Power Bandwidth
Peak Slew Rate
Sinusoid Amplitude
=
××
()
2
π
Peak slew rate is not the same as average slew rate (25% to 75%)
as typically specified. For a natural response, peak slew rate
may be 2.7 times larger than average slew rate. Therefore, calcu-
lating a full power bandwidth with a specified average slew rate
will give a pessimistic result.
APPLICATIONS
Driving Capacitive Loads
When driving a large capacitive load, most amplifiers will exhibit
peaking/ringing in pulse response. To minimize peaking, and to
ensure stability for larger values of capacitive loads, a small
resistor, RS, can be added between the output and the load
capacitor, CL. This is shown in Figure 39.
5ns
0.5V
0.0V
–0.5V
250mV
RS = 0 , CL = 5pF
RS = 15 , CL = 20pF
RS = 20 , CL = 20pF
CL
1k
VIN
VOUT
RS
75
Figure 39. Pulse Responses Driving Capacitive Loads
Power Supply and Layout Considerations
The AD8183 and AD8185 are very high performance muxes
that require attention to several important design details to real-
ize their specified performance. Good high-frequency layout
rules must be carefully observed.
A good design will start with a solid ground plane. All the GND
pins of the part(s) should be directly connected to it. In addi-
tion, bypass capacitors should be connected from each supply
pin (VCC and VEE) to the ground plane. It is suggested to use
0.01
F surface-mount chip capacitors as close to the IC as
possible to provide high-frequency bypassing.
For lower frequency bypassing, higher value tantalum capacitors—
at least 10
F—should be provided from both V
CC and VEE to
ground. These do not have to be as close to the IC pins, because
parasitic inductance is not as big a factor at low frequencies.
Please refer to AD8183/AD8185 Evaluation Board Operation
Guide for further information.
Crosstalk
In normal operation the AD8183 and AD8185 will have signals
at some of the input pins that are not switched to appear at the
output. In addition, several signal paths will in general be active
at one time. In any system that has high-frequency signals that
are brought together in close proximity, there will be inevitable
crosstalk, whereby some fraction of the undesired signals will
appear at the outputs. This can result, for example, in ghost images
in an RGB monitor muxing application.
The AD8183 and AD8185 are capable of excellent low-
crosstalk performance. However, in order to realize the best
possible crosstalk performance, certain design details should be
followed. Most of the low-crosstalk specification is inherent in
the part and will result from observing the power supply and
layout consideration discussed above. This is because each of
the input and output pins are separated by at least either a
supply pin or a ground pin.
This package architecture helps the crosstalk performance in at
least three ways. First, the supply and ground pins provide extra
physical separation between the input- and output-signal pins.
Physical separation is a very effective technique for reducing
crosstalk.
Second, the supply and ground pins are at ac ground, and there-
fore provide a degree of shielding between the signals. This
works for both capacitive crosstalk, which is due to voltages on
the signals, and inductive crosstalk, which is due to currents that
flow through the signal paths.
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| AD8185ARUZ | 功能描述:IC MULTIPLEXER TRPL 2X1 24TSSOP RoHS:是 類別:集成電路 (IC) >> 接口 - 模擬開關，多路復用器，多路分解器 系列:- 其它有關文件:STG4159 View All Specifications 標準包裝:5,000 系列:- 功能:開關 電路:1 x SPDT 導通狀態(tài)電阻:300 毫歐 電壓電源:雙電源 電壓 - 電源，單路/雙路(±):±1.65 V ~ 4.8 V 電流 - 電源:50nA 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:7-WFBGA，F(xiàn)CBGA 供應商設備封裝:7-覆晶 包裝:帶卷 (TR) |
| AD8185ARUZ-REEL | 功能描述:IC MULTIPLEXER TRPL 2X1 24TSSOP RoHS:是 類別:集成電路 (IC) >> 接口 - 模擬開關，多路復用器，多路分解器 系列:- 其它有關文件:STG4159 View All Specifications 標準包裝:5,000 系列:- 功能:開關 電路:1 x SPDT 導通狀態(tài)電阻:300 毫歐 電壓電源:雙電源 電壓 - 電源，單路/雙路(±):±1.65 V ~ 4.8 V 電流 - 電源:50nA 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:7-WFBGA，F(xiàn)CBGA 供應商設備封裝:7-覆晶 包裝:帶卷 (TR) |
| AD8185ARUZ-REEL7 | 功能描述:IC MULTIPLEXER TRPL 2X1 24TSSOP RoHS:是 類別:集成電路 (IC) >> 接口 - 模擬開關，多路復用器，多路分解器 系列:- 其它有關文件:STG4159 View All Specifications 標準包裝:5,000 系列:- 功能:開關 電路:1 x SPDT 導通狀態(tài)電阻:300 毫歐 電壓電源:雙電源 電壓 - 電源，單路/雙路(±):±1.65 V ~ 4.8 V 電流 - 電源:50nA 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:7-WFBGA，F(xiàn)CBGA 供應商設備封裝:7-覆晶 包裝:帶卷 (TR) |
| AD8185-EVAL | 制造商:Analog Devices 功能描述:AD8185 EVALUATION BOARD - Bulk |
| AD8186 | 制造商:AD 制造商全稱:Analog Devices 功能描述:480 MHz Single-Supply (5 V) Triple 2:1 Multiplexers |
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