
REV. A
–14–
AD8152
CS
WE
A[6:0]INPUTS
D[5:0]INPUTS
tCSW
tASW
tWP
tDSW
tAHW
tCHW
tDHW
Figure 3a. First Rank Write Cycle
Table V. First Rank Write Cycle
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
tCSW
Setup Time
Chip Select to Write Enable
TA = 25 C0
ns
tASW
Address to Write Enable
0
ns
tDSW
Data to Write Enable
VCC = 3.3 V
1
ns
tCHW
Hold Time
Chip Select from Write Enable
0
ns
tAHW
Address from Write Enable
0
ns
tDHW
Data from Write Enable
0
ns
tWP
Width of Write Enable Pulse
10
ns
CS
UPDATE
ENABLING
OUT[0:33][N:P]
OUTPUTS
TOGGLE
OUT[0:33][N:P]
OUTPUTS
DATA FROM RANK 1
tCSU
tUOE
tUW
tCHU
DISABLING
OUT[0:33][N:P]
OUTPUTS
tUOD
DATA FROM RANK 1
DATA FROM RANK 2
PREVIOUS RANK 2 DATA
tUOT
Figure 3b. Second Rank Update Cycle
Table VI. Second Rank Update Cycle
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
tCSU
Setup Time
Chip Select to Update
TA = 25 C0
ns
tCHU
Hold Time
Chip Select from Update
0
ns
tUOE
Output Enable Times
Update to Output Enable
VCC = 3.3 V
25
45
ns
tUOT
Output Toggle Times
Update to Output Reprogram
25
45
ns
tUOD
Output Disable Times
Update to Output Disabled
25
45
ns
tUW
Width of Update Pulse
10
ns