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參數(shù)資料
| 型號(hào)： | AD8128ACPZ-RL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類(lèi)： | 模擬信號(hào)調(diào)理 |
| 英文描述： | CAT-5 Receiver with Adjustable Line Equalization |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, DSO8 |
| 封裝： | 3 X 3 MM, LEAD FREE, LFCSP-8 |
| 文件頁(yè)數(shù)： | 7/12頁(yè) |
| 文件大?。?/td> | 241K |
| 代理商： | AD8128ACPZ-RL |
AD8128
Rev. 0 | Page 7 of 12
1.5
–1.5
0
200
0
TIME (ns)
O
1.0
0.5
0
–0.5
–1.0
20
40
60
80
100
120
140
160
180
V
AND V
SETTINGSARE
CONSISTENT WITH OPTIMIZED
SETTINGS IN FIGURE 4
Figure 10. Equalized Pulse Response for 100 M of Cable
40
–40
–4
4
0
V
IN, CM
(V)
V
O
(
30
20
10
0
–10
–20
–30
–3
–2
–1
0
1
2
3
Figure 11. Output Voltage vs. Common-Mode Input Voltage
100
10
0.1
1k
0
FREQUENCY (MHz)
V
1
10
100
V
PEAK
= 0V
V
GAIN
= 0V
V
PEAK
= 0.9V
V
GAIN
= 0.225V
Figure 12. Voltage Noise vs. Frequency
1.8
0
0
1.0
0
V
PEAK
(V)
I
1
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
V
SETTINGS ARE CONSISTENT
WITH OPTIMIZED SETTINGS IN FIGURE 4
Figure 13. Integrated Voltage Noise vs. V
PEAK
6
–6
0
500
0
TIME (ns)
V
4
2
0
–2
–4
50
100
150
200
250
300
350
400
450
V
PEAK
= 0V
V
GAIN
= 0V
OUTPUT
INPUT
Figure 14. Overdrive Recovery Time
20
–80
0.1
1k
0
FREQUENCY (MHz)
C
1
10
100
10
0
–10
–20
–30
–40
–50
–60
–70
V
GAIN
= 1V
V
PEAK
= 1V
V
GAIN
= 0V
V
PEAK
= 0V
Figure 15. Common-Mode Rejection vs. Frequency
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